| Message ID | 1458762429-9397-1-git-send-email-srinivas.kandagatla@linaro.org (mailing list archive) |
|---|---|
| State | Superseded, archived |
| Delegated to: | Andy Gross |
| Headers | show |
On Wed 23 Mar 12:47 PDT 2016, Srinivas Kandagatla wrote: > This patch adds support to gsbi1 uart and its pinctrls nodes. > > Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> > --- > arch/arm/boot/dts/qcom-apq8064-pins.dtsi | 14 ++++++++++++++ > arch/arm/boot/dts/qcom-apq8064.dtsi | 10 ++++++++++ > 2 files changed, 24 insertions(+) > > diff --git a/arch/arm/boot/dts/qcom-apq8064-pins.dtsi b/arch/arm/boot/dts/qcom-apq8064-pins.dtsi > index b57c59d..8bb5e5f 100644 > --- a/arch/arm/boot/dts/qcom-apq8064-pins.dtsi > +++ b/arch/arm/boot/dts/qcom-apq8064-pins.dtsi > @@ -39,6 +39,20 @@ > }; > }; > > + gsbi1_uart_2pins: gsbi1_uart_2pins { > + mux { > + pins = "gpio18", "gpio19"; > + function = "gsbi1"; > + }; > + }; > + > + gsbi1_uart_4pins: gsbi1_uart_4pins { > + mux { > + pins = "gpio18", "gpio19", "gpio20", "gpio21"; > + function = "gsbi1"; > + }; > + }; > + No-one consumes this nodes. > i2c2_pins: i2c2 { > mux { > pins = "gpio24", "gpio25"; > diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi > index c6ff8fc..81b4290 100644 > --- a/arch/arm/boot/dts/qcom-apq8064.dtsi > +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi > @@ -225,6 +225,16 @@ > > syscon-tcsr = <&tcsr>; > > + gsbi1_serial: serial@12450000 { Are you going to reference this node? Otherwise it should not have a label. > + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; > + reg = <0x12450000 0x100>, > + <0x12400000 0x03>; > + interrupts = <0 193 0x0>; > + clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>; > + clock-names = "core", "iface"; > + status = "disabled"; > + }; > + Regards, Bjorn -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/arch/arm/boot/dts/qcom-apq8064-pins.dtsi b/arch/arm/boot/dts/qcom-apq8064-pins.dtsi index b57c59d..8bb5e5f 100644 --- a/arch/arm/boot/dts/qcom-apq8064-pins.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064-pins.dtsi @@ -39,6 +39,20 @@ }; }; + gsbi1_uart_2pins: gsbi1_uart_2pins { + mux { + pins = "gpio18", "gpio19"; + function = "gsbi1"; + }; + }; + + gsbi1_uart_4pins: gsbi1_uart_4pins { + mux { + pins = "gpio18", "gpio19", "gpio20", "gpio21"; + function = "gsbi1"; + }; + }; + i2c2_pins: i2c2 { mux { pins = "gpio24", "gpio25"; diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index c6ff8fc..81b4290 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -225,6 +225,16 @@ syscon-tcsr = <&tcsr>; + gsbi1_serial: serial@12450000 { + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; + reg = <0x12450000 0x100>, + <0x12400000 0x03>; + interrupts = <0 193 0x0>; + clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + gsbi1_i2c: i2c@12460000 { compatible = "qcom,i2c-qup-v1.1.1"; pinctrl-0 = <&i2c1_pins>;
This patch adds support to gsbi1 uart and its pinctrls nodes. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> --- arch/arm/boot/dts/qcom-apq8064-pins.dtsi | 14 ++++++++++++++ arch/arm/boot/dts/qcom-apq8064.dtsi | 10 ++++++++++ 2 files changed, 24 insertions(+)