diff mbox

[v3,3/8] clk: samsung: exynos3250: Add MMC2 clock

Message ID 1458027490-13787-4-git-send-email-cw00.choi@samsung.com (mailing list archive)
State New, archived
Headers show

Commit Message

Chanwoo Choi March 15, 2016, 7:38 a.m. UTC 
This patch add the MMC2 clocks (mux, divider, gate) of Exynos3250 SoC.

Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
---
 drivers/clk/samsung/clk-exynos3250.c   | 9 +++++++++
 include/dt-bindings/clock/exynos3250.h | 7 ++++++-
 2 files changed, 15 insertions(+), 1 deletion(-)

Comments

Chanwoo Choi March 24, 2016, 11:39 p.m. UTC | #1 
Ping.

Hi Sylwester,

Could you review this patch?

Regards,
Chanwoo Choi

On 2016? 03? 15? 16:38, Chanwoo Choi wrote:
> This patch add the MMC2 clocks (mux, divider, gate) of Exynos3250 SoC.
> 
> Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
> Cc: Tomasz Figa <tomasz.figa@gmail.com>
> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
> ---
>  drivers/clk/samsung/clk-exynos3250.c   | 9 +++++++++
>  include/dt-bindings/clock/exynos3250.h | 7 ++++++-
>  2 files changed, 15 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/samsung/clk-exynos3250.c b/drivers/clk/samsung/clk-exynos3250.c
> index bc60e399d1bc..16575ee874cb 100644
> --- a/drivers/clk/samsung/clk-exynos3250.c
> +++ b/drivers/clk/samsung/clk-exynos3250.c
> @@ -302,6 +302,7 @@ static struct samsung_mux_clock mux_clks[] __initdata = {
>  
>  	/* SRC_FSYS */
>  	MUX(CLK_MOUT_TSADC, "mout_tsadc", group_sclk_p, SRC_FSYS, 28, 4),
> +	MUX(CLK_MOUT_MMC2, "mout_mmc2", group_sclk_p, SRC_FSYS, 8, 4),
>  	MUX(CLK_MOUT_MMC1, "mout_mmc1", group_sclk_p, SRC_FSYS, 4, 4),
>  	MUX(CLK_MOUT_MMC0, "mout_mmc0", group_sclk_p, SRC_FSYS, 0, 4),
>  
> @@ -390,6 +391,11 @@ static struct samsung_div_clock div_clks[] __initdata = {
>  		CLK_SET_RATE_PARENT, 0),
>  	DIV(CLK_DIV_MMC0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
>  
> +	/* DIV_FSYS2 */
> +	DIV_F(CLK_DIV_MMC2_PRE, "div_mmc2_pre", "div_mmc2", DIV_FSYS2, 8, 8,
> +		CLK_SET_RATE_PARENT, 0),
> +	DIV(CLK_DIV_MMC2, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4),
> +
>  	/* DIV_PERIL0 */
>  	DIV(CLK_DIV_UART2, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4),
>  	DIV(CLK_DIV_UART1, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4),
> @@ -540,6 +546,8 @@ static struct samsung_gate_clock gate_clks[] __initdata = {
>  		GATE_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0),
>  	GATE(CLK_SCLK_EBI, "sclk_ebi", "div_ebi",
>  		GATE_SCLK_FSYS, 6, CLK_SET_RATE_PARENT, 0),
> +	GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc2_pre",
> +		GATE_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0),
>  	GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc1_pre",
>  		GATE_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0),
>  	GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc0_pre",
> @@ -635,6 +643,7 @@ static struct samsung_gate_clock gate_clks[] __initdata = {
>  	GATE(CLK_USBOTG, "usbotg", "div_aclk_200", GATE_IP_FSYS, 13, 0, 0),
>  	GATE(CLK_USBHOST, "usbhost", "div_aclk_200", GATE_IP_FSYS, 12, 0, 0),
>  	GATE(CLK_SROMC, "sromc", "div_aclk_200", GATE_IP_FSYS, 11, 0, 0),
> +	GATE(CLK_SDMMC2, "sdmmc2", "div_aclk_200", GATE_IP_FSYS, 7, 0, 0),
>  	GATE(CLK_SDMMC1, "sdmmc1", "div_aclk_200", GATE_IP_FSYS, 6, 0, 0),
>  	GATE(CLK_SDMMC0, "sdmmc0", "div_aclk_200", GATE_IP_FSYS, 5, 0, 0),
>  	GATE(CLK_PDMA1, "pdma1", "div_aclk_200", GATE_IP_FSYS, 1, 0, 0),
> diff --git a/include/dt-bindings/clock/exynos3250.h b/include/dt-bindings/clock/exynos3250.h
> index ddb874130d86..c796ff02ceeb 100644
> --- a/include/dt-bindings/clock/exynos3250.h
> +++ b/include/dt-bindings/clock/exynos3250.h
> @@ -80,6 +80,7 @@
>  #define CLK_MOUT_APLL			59
>  #define CLK_MOUT_ACLK_266_SUB		60
>  #define CLK_MOUT_UART2			61
> +#define CLK_MOUT_MMC2			62
>  
>  /* Dividers */
>  #define CLK_DIV_GPL			64
> @@ -129,6 +130,8 @@
>  #define CLK_DIV_HPM			108
>  #define CLK_DIV_COPY			109
>  #define CLK_DIV_UART2			110
> +#define CLK_DIV_MMC2_PRE		111
> +#define CLK_DIV_MMC2			112
>  
>  /* Gates */
>  #define CLK_ASYNC_G3D			128
> @@ -226,6 +229,7 @@
>  #define CLK_BLOCK_CAM			220
>  #define CLK_SMIES			221
>  #define CLK_UART2			222
> +#define CLK_SDMMC2			223
>  
>  /* Special clocks */
>  #define CLK_SCLK_JPEG			224
> @@ -253,12 +257,13 @@
>  #define CLK_SCLK_UART1			246
>  #define CLK_SCLK_UART0			247
>  #define CLK_SCLK_UART2			248
> +#define CLK_SCLK_MMC2			249
>  
>  /*
>   * Total number of clocks of main CMU.
>   * NOTE: Must be equal to last clock ID increased by one.
>   */
> -#define CLK_NR_CLKS			249
> +#define CLK_NR_CLKS			250
>  
>  /*
>   * CMU DMC
>
Sylwester Nawrocki/Kernel \(PLT\) /SRPOL/Staff Engineer/Samsung Electronics March 25, 2016, 9:50 a.m. UTC | #2 
Hi Chanwoo,

On 03/25/2016 12:39 AM, Chanwoo Choi wrote:
> diff --git a/include/dt-bindings/clock/exynos3250.h 
> b/include/dt-bindings/clock/exynos3250.h
>> index ddb874130d86..c796ff02ceeb 100644
>> --- a/include/dt-bindings/clock/exynos3250.h
>> +++ b/include/dt-bindings/clock/exynos3250.h
...
>> -#define CLK_NR_CLKS			249
>> +#define CLK_NR_CLKS			250

What do you think about putting all the changes to include/dt-bindings/
clock/exynos3250.h into a separate patch? Now in patch 3/8 there
is being changed again what was added in patch 2/8. However, my main
point is to have a minimum required in a common topic branch for the clk
and the arm-soc trees, so there is no need for arm-soc to pull all
the drives/clk changes.
It might not be that sensible in case of just those 2 patches in your
series, nevertheless it would be good to keep that in mind for future
submissions.

--
Thanks,
Sylwester
Chanwoo Choi March 28, 2016, 12:44 a.m. UTC | #3 
Hi Sylwester,

On 2016? 03? 25? 18:50, Sylwester Nawrocki wrote:
> Hi Chanwoo,
> 
> On 03/25/2016 12:39 AM, Chanwoo Choi wrote:
>> diff --git a/include/dt-bindings/clock/exynos3250.h 
>> b/include/dt-bindings/clock/exynos3250.h
>>> index ddb874130d86..c796ff02ceeb 100644
>>> --- a/include/dt-bindings/clock/exynos3250.h
>>> +++ b/include/dt-bindings/clock/exynos3250.h
> ...
>>> -#define CLK_NR_CLKS			249
>>> +#define CLK_NR_CLKS			250
> 
> What do you think about putting all the changes to include/dt-bindings/
> clock/exynos3250.h into a separate patch? Now in patch 3/8 there
> is being changed again what was added in patch 2/8. However, my main
> point is to have a minimum required in a common topic branch for the clk
> and the arm-soc trees, so there is no need for arm-soc to pull all
> the drives/clk changes.
> It might not be that sensible in case of just those 2 patches in your
> series, nevertheless it would be good to keep that in mind for future
> submissions.

You mean that separate patch1 include only the new clock id about both UART2 and MMC2
and the patch2/patch3 just use the new clock id as following:

patch1 dt-bindings: Add the clock id of UART2 and MMC2 for Exynos3250
patch2 clk: samsung: exynos3250: Add UART2 clock
patch3 clk: samsung: exynos3250: Add MMC2 clock

As far as I understand it is that right?
If it is ok, I'll modify it on v4 patchset as you comment.

Best Regards,
Chanwoo Choi
Krzysztof Kozlowski March 29, 2016, 1:48 a.m. UTC | #4 
On 28.03.2016 09:44, Chanwoo Choi wrote:
> You mean that separate patch1 include only the new clock id about both UART2 and MMC2
> and the patch2/patch3 just use the new clock id as following:
> 
> patch1 dt-bindings: Add the clock id of UART2 and MMC2 for Exynos3250
> patch2 clk: samsung: exynos3250: Add UART2 clock
> patch3 clk: samsung: exynos3250: Add MMC2 clock
> 
> As far as I understand it is that right?
> If it is ok, I'll modify it on v4 patchset as you comment.

Hi Sylwester and Tomasz,

Can you provide me a tag with these exynos3250 clock patches (after
posting v4)? Of course you can also ack/review them and then I'll handle it.

BR,
Krzysztof
Sylwester Nawrocki/Kernel \(PLT\) /SRPOL/Staff Engineer/Samsung Electronics March 30, 2016, 9:30 a.m. UTC | #5 
On 03/28/2016 02:44 AM, Chanwoo Choi wrote:
> You mean that separate patch1 include only the new clock id about both UART2 and MMC2
> and the patch2/patch3 just use the new clock id as following:
> 
> patch1 dt-bindings: Add the clock id of UART2 and MMC2 for Exynos3250
> patch2 clk: samsung: exynos3250: Add UART2 clock
> patch3 clk: samsung: exynos3250: Add MMC2 clock
> 
> As far as I understand it is that right?
> If it is ok, I'll modify it on v4 patchset as you comment.

Yeah, that's what I meant.
Sylwester Nawrocki/Kernel \(PLT\) /SRPOL/Staff Engineer/Samsung Electronics March 30, 2016, 9:37 a.m. UTC | #6 
On 03/29/2016 03:48 AM, Krzysztof Kozlowski wrote:
> On 28.03.2016 09:44, Chanwoo Choi wrote:
>> > You mean that separate patch1 include only the new clock id about both UART2 and MMC2
>> > and the patch2/patch3 just use the new clock id as following:
>> > 
>> > patch1 dt-bindings: Add the clock id of UART2 and MMC2 for Exynos3250
>> > patch2 clk: samsung: exynos3250: Add UART2 clock
>> > patch3 clk: samsung: exynos3250: Add MMC2 clock
>> > 
>> > As far as I understand it is that right?
>> > If it is ok, I'll modify it on v4 patchset as you comment.
>
> Hi Sylwester and Tomasz,
> 
> Can you provide me a tag with these exynos3250 clock patches (after
> posting v4)? Of course you can also ack/review them and then I'll handle it.

OK, I will provide a stable branch as soon as there is v4 available.
Krzysztof Kozlowski April 1, 2016, 12:15 a.m. UTC | #7 
On 31.03.2016 20:04, Sylwester Nawrocki wrote:
> On 03/29/2016 03:48 AM, Krzysztof Kozlowski wrote:
>> On 28.03.2016 09:44, Chanwoo Choi wrote:
>>> You mean that separate patch1 include only the new clock id 
>>> about both UART2 and MMC2
>>> and the patch2/patch3 just use the new clock id as following:
>>>
>>> patch1 dt-bindings: Add the clock id of UART2 and MMC2 for Exynos3250
>>> patch2 clk: samsung: exynos3250: Add UART2 clock
>>> patch3 clk: samsung: exynos3250: Add MMC2 clock
>>>
>>> As far as I understand it is that right?
>>> If it is ok, I'll modify it on v4 patchset as you comment.
>>
>> Hi Sylwester and Tomasz,
>>
>> Can you provide me a tag with these exynos3250 clock patches (after
>> posting v4)? Of course you can also ack/review them and then I'll 
>> handle it.
> 
> Here are tags with only the first (clock id definitions) and the all 
> three clk patches respectively:
> 
> ---------------------------------------8<--------------------------------
> The following changes since commit f55532a0c0b8bb6148f4e07853b876ef73bc69ca:
> 
>   Linux 4.6-rc1 (2016-03-26 16:03:24 -0700)
> 
> are available in the git repository at:
> 
>   git://linuxtv.org/snawrocki/samsung.git tags/clk-v4.7-exynos3250-dt
> 
> for you to fetch changes up to fd00bbcddb59c4866e7c985e30f663b62cfc2588:
> 
>   dt-bindings: Add the clock id of UART2 and MMC2 for Exynos3250 (2016-03-31 12:25:44 +0200)
> 
> ----------------------------------------------------------------
> Addition of the UART2 and MMC3 clock indices definition
> to the exynos3250 clock subsystem dt binding header file.
> 
> ----------------------------------------------------------------
> Chanwoo Choi (1):
>       dt-bindings: Add the clock id of UART2 and MMC2 for Exynos3250
> 
>  include/dt-bindings/clock/exynos3250.h | 11 ++++++++++-
>  1 file changed, 10 insertions(+), 1 deletion(-)
> --------------------------------------->8--------------------------------
> 
> 
> ---------------------------------------8<--------------------------------
> The following changes since commit f55532a0c0b8bb6148f4e07853b876ef73bc69ca:
> 
>   Linux 4.6-rc1 (2016-03-26 16:03:24 -0700)
> 
> are available in the git repository at:
> 
>   git://linuxtv.org/snawrocki/samsung.git tags/clk-v4.7-exynos3250

Thanks pulled.

Krzysztof
diff mbox

Patch

diff --git a/drivers/clk/samsung/clk-exynos3250.c b/drivers/clk/samsung/clk-exynos3250.c
index bc60e399d1bc..16575ee874cb 100644
--- a/drivers/clk/samsung/clk-exynos3250.c
+++ b/drivers/clk/samsung/clk-exynos3250.c
@@ -302,6 +302,7 @@  static struct samsung_mux_clock mux_clks[] __initdata = {
 
 	/* SRC_FSYS */
 	MUX(CLK_MOUT_TSADC, "mout_tsadc", group_sclk_p, SRC_FSYS, 28, 4),
+	MUX(CLK_MOUT_MMC2, "mout_mmc2", group_sclk_p, SRC_FSYS, 8, 4),
 	MUX(CLK_MOUT_MMC1, "mout_mmc1", group_sclk_p, SRC_FSYS, 4, 4),
 	MUX(CLK_MOUT_MMC0, "mout_mmc0", group_sclk_p, SRC_FSYS, 0, 4),
 
@@ -390,6 +391,11 @@  static struct samsung_div_clock div_clks[] __initdata = {
 		CLK_SET_RATE_PARENT, 0),
 	DIV(CLK_DIV_MMC0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
 
+	/* DIV_FSYS2 */
+	DIV_F(CLK_DIV_MMC2_PRE, "div_mmc2_pre", "div_mmc2", DIV_FSYS2, 8, 8,
+		CLK_SET_RATE_PARENT, 0),
+	DIV(CLK_DIV_MMC2, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4),
+
 	/* DIV_PERIL0 */
 	DIV(CLK_DIV_UART2, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4),
 	DIV(CLK_DIV_UART1, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4),
@@ -540,6 +546,8 @@  static struct samsung_gate_clock gate_clks[] __initdata = {
 		GATE_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0),
 	GATE(CLK_SCLK_EBI, "sclk_ebi", "div_ebi",
 		GATE_SCLK_FSYS, 6, CLK_SET_RATE_PARENT, 0),
+	GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc2_pre",
+		GATE_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0),
 	GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc1_pre",
 		GATE_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0),
 	GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc0_pre",
@@ -635,6 +643,7 @@  static struct samsung_gate_clock gate_clks[] __initdata = {
 	GATE(CLK_USBOTG, "usbotg", "div_aclk_200", GATE_IP_FSYS, 13, 0, 0),
 	GATE(CLK_USBHOST, "usbhost", "div_aclk_200", GATE_IP_FSYS, 12, 0, 0),
 	GATE(CLK_SROMC, "sromc", "div_aclk_200", GATE_IP_FSYS, 11, 0, 0),
+	GATE(CLK_SDMMC2, "sdmmc2", "div_aclk_200", GATE_IP_FSYS, 7, 0, 0),
 	GATE(CLK_SDMMC1, "sdmmc1", "div_aclk_200", GATE_IP_FSYS, 6, 0, 0),
 	GATE(CLK_SDMMC0, "sdmmc0", "div_aclk_200", GATE_IP_FSYS, 5, 0, 0),
 	GATE(CLK_PDMA1, "pdma1", "div_aclk_200", GATE_IP_FSYS, 1, 0, 0),
diff --git a/include/dt-bindings/clock/exynos3250.h b/include/dt-bindings/clock/exynos3250.h
index ddb874130d86..c796ff02ceeb 100644
--- a/include/dt-bindings/clock/exynos3250.h
+++ b/include/dt-bindings/clock/exynos3250.h
@@ -80,6 +80,7 @@ 
 #define CLK_MOUT_APLL			59
 #define CLK_MOUT_ACLK_266_SUB		60
 #define CLK_MOUT_UART2			61
+#define CLK_MOUT_MMC2			62
 
 /* Dividers */
 #define CLK_DIV_GPL			64
@@ -129,6 +130,8 @@ 
 #define CLK_DIV_HPM			108
 #define CLK_DIV_COPY			109
 #define CLK_DIV_UART2			110
+#define CLK_DIV_MMC2_PRE		111
+#define CLK_DIV_MMC2			112
 
 /* Gates */
 #define CLK_ASYNC_G3D			128
@@ -226,6 +229,7 @@ 
 #define CLK_BLOCK_CAM			220
 #define CLK_SMIES			221
 #define CLK_UART2			222
+#define CLK_SDMMC2			223
 
 /* Special clocks */
 #define CLK_SCLK_JPEG			224
@@ -253,12 +257,13 @@ 
 #define CLK_SCLK_UART1			246
 #define CLK_SCLK_UART0			247
 #define CLK_SCLK_UART2			248
+#define CLK_SCLK_MMC2			249
 
 /*
  * Total number of clocks of main CMU.
  * NOTE: Must be equal to last clock ID increased by one.
  */
-#define CLK_NR_CLKS			249
+#define CLK_NR_CLKS			250
 
 /*
  * CMU DMC