| Message ID | 1458158097-21137-3-git-send-email-t-kristo@ti.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 03/16, Tero Kristo wrote: > AM33xx/AM43xx devices use the same DPLL IP blocks, which only support > maximum rate of 1GHz [1] for the default and 2GHz for the low-jitter type > DPLLs [2]. Reflect this limitation in the DPLL init code by adding the > max-rate parameter based on the DPLL types. > > [1] Functional, integration & test specification for GS70 ADPLLS, Rev 1.0-01 > [2] Functional, integration & test specification for GS70 ADPLLLJ, Rev 0.8-02 > > Signed-off-by: Tero Kristo <t-kristo@ti.com> > Cc: Nishanth Menon <nm@ti.com> > Cc: Tomi Valkeinen <tomi.valkeinen@ti.com> > Cc: Lokesh Vutla <lokeshvutla@ti.com> > --- Acked-by: Stephen Boyd <sboyd@codeaurora.org> Or I can apply these two targeting 4.7 if you like.
On 04/01/2016 10:28 PM, Stephen Boyd wrote: > On 03/16, Tero Kristo wrote: >> AM33xx/AM43xx devices use the same DPLL IP blocks, which only support >> maximum rate of 1GHz [1] for the default and 2GHz for the low-jitter type >> DPLLs [2]. Reflect this limitation in the DPLL init code by adding the >> max-rate parameter based on the DPLL types. >> >> [1] Functional, integration & test specification for GS70 ADPLLS, Rev 1.0-01 >> [2] Functional, integration & test specification for GS70 ADPLLLJ, Rev 0.8-02 >> >> Signed-off-by: Tero Kristo <t-kristo@ti.com> >> Cc: Nishanth Menon <nm@ti.com> >> Cc: Tomi Valkeinen <tomi.valkeinen@ti.com> >> Cc: Lokesh Vutla <lokeshvutla@ti.com> >> --- > > Acked-by: Stephen Boyd <sboyd@codeaurora.org> > > Or I can apply these two targeting 4.7 if you like. Yea I am fine with this. Want to pick up the old patch from Grygorii also? -Tero
On 04/13, Tero Kristo wrote: > On 04/01/2016 10:28 PM, Stephen Boyd wrote: > >On 03/16, Tero Kristo wrote: > >>AM33xx/AM43xx devices use the same DPLL IP blocks, which only support > >>maximum rate of 1GHz [1] for the default and 2GHz for the low-jitter type > >>DPLLs [2]. Reflect this limitation in the DPLL init code by adding the > >>max-rate parameter based on the DPLL types. > >> > >>[1] Functional, integration & test specification for GS70 ADPLLS, Rev 1.0-01 > >>[2] Functional, integration & test specification for GS70 ADPLLLJ, Rev 0.8-02 > >> > >>Signed-off-by: Tero Kristo <t-kristo@ti.com> > >>Cc: Nishanth Menon <nm@ti.com> > >>Cc: Tomi Valkeinen <tomi.valkeinen@ti.com> > >>Cc: Lokesh Vutla <lokeshvutla@ti.com> > >>--- > > > >Acked-by: Stephen Boyd <sboyd@codeaurora.org> > > > >Or I can apply these two targeting 4.7 if you like. > > Yea I am fine with this. Want to pick up the old patch from Grygorii also? > Ok let me find these two!
On 03/16, Tero Kristo wrote: > AM33xx/AM43xx devices use the same DPLL IP blocks, which only support > maximum rate of 1GHz [1] for the default and 2GHz for the low-jitter type > DPLLs [2]. Reflect this limitation in the DPLL init code by adding the > max-rate parameter based on the DPLL types. > > [1] Functional, integration & test specification for GS70 ADPLLS, Rev 1.0-01 > [2] Functional, integration & test specification for GS70 ADPLLLJ, Rev 0.8-02 > > Signed-off-by: Tero Kristo <t-kristo@ti.com> > Cc: Nishanth Menon <nm@ti.com> > Cc: Tomi Valkeinen <tomi.valkeinen@ti.com> > Cc: Lokesh Vutla <lokeshvutla@ti.com> > --- Applied to clk-next
diff --git a/drivers/clk/ti/dpll.c b/drivers/clk/ti/dpll.c index 5519b38..4caadb9 100644 --- a/drivers/clk/ti/dpll.c +++ b/drivers/clk/ti/dpll.c @@ -642,6 +642,7 @@ static void __init of_ti_am3_no_gate_dpll_setup(struct device_node *node) .max_multiplier = 2047, .max_divider = 128, .min_divider = 1, + .max_rate = 1000000000, .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), }; @@ -661,6 +662,7 @@ static void __init of_ti_am3_jtype_dpll_setup(struct device_node *node) .max_divider = 256, .min_divider = 2, .flags = DPLL_J_TYPE, + .max_rate = 2000000000, .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), }; @@ -679,6 +681,7 @@ static void __init of_ti_am3_no_gate_jtype_dpll_setup(struct device_node *node) .max_multiplier = 2047, .max_divider = 128, .min_divider = 1, + .max_rate = 2000000000, .flags = DPLL_J_TYPE, .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), }; @@ -699,6 +702,7 @@ static void __init of_ti_am3_dpll_setup(struct device_node *node) .max_multiplier = 2047, .max_divider = 128, .min_divider = 1, + .max_rate = 1000000000, .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), }; @@ -716,6 +720,7 @@ static void __init of_ti_am3_core_dpll_setup(struct device_node *node) .max_multiplier = 2047, .max_divider = 128, .min_divider = 1, + .max_rate = 1000000000, .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), };
AM33xx/AM43xx devices use the same DPLL IP blocks, which only support maximum rate of 1GHz [1] for the default and 2GHz for the low-jitter type DPLLs [2]. Reflect this limitation in the DPLL init code by adding the max-rate parameter based on the DPLL types. [1] Functional, integration & test specification for GS70 ADPLLS, Rev 1.0-01 [2] Functional, integration & test specification for GS70 ADPLLLJ, Rev 0.8-02 Signed-off-by: Tero Kristo <t-kristo@ti.com> Cc: Nishanth Menon <nm@ti.com> Cc: Tomi Valkeinen <tomi.valkeinen@ti.com> Cc: Lokesh Vutla <lokeshvutla@ti.com> --- drivers/clk/ti/dpll.c | 5 +++++ 1 file changed, 5 insertions(+)