diff mbox

[v3] drm/i915: resize the GuC WOPCM for rc6

Message ID 1461661901-8448-1-git-send-email-peter.antoine@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Peter Antoine April 26, 2016, 9:11 a.m. UTC 
This patch resizes the GuC WOPCM to so that the GuC and the RC6 memory
spaces do not overlap.

Issue: https://jira01.devtools.intel.com/browse/VIZ-6638
Signed-off-by: Peter Antoine <peter.antoine@intel.com>
---
 drivers/gpu/drm/i915/i915_guc_reg.h     | 5 +++--
 drivers/gpu/drm/i915/intel_guc_loader.c | 6 +++++-
 2 files changed, 8 insertions(+), 3 deletions(-)

Comments

Peter Antoine April 26, 2016, 10:38 a.m. UTC | #1 
On Tue, 26 Apr 2016, Patchwork wrote:

> == Series Details ==
>
> Series: drm/i915: resize the GuC WOPCM for rc6
> URL   : https://patchwork.freedesktop.org/series/6313/
> State : failure
>
> == Summary ==
>
> Series 6313v1 drm/i915: resize the GuC WOPCM for rc6
> http://patchwork.freedesktop.org/api/1.0/series/6313/revisions/1/mbox/
>
> Test kms_flip:
>        Subgroup basic-flip-vs-wf_vblank:
>                pass       -> FAIL       (hsw-gt2)
Patch cannot effect HSW as platform does not have GuC and GuC code is all 
guarded by platform. False Failure.

> Test kms_force_connector_basic:
>        Subgroup force-edid:
>                pass       -> SKIP       (ivb-t430s)
Nothing to do with display.

> Test kms_pipe_crc_basic:
>        Subgroup read-crc-pipe-b-frame-sequence:
>                skip       -> PASS       (bdw-nuci7)
Same.

>
> bdw-nuci7        total:200  pass:188  dwarn:0   dfail:0   fail:0   skip:12
> bdw-ultra        total:200  pass:175  dwarn:0   dfail:0   fail:0   skip:25
> bsw-nuc-2        total:199  pass:158  dwarn:0   dfail:0   fail:0   skip:41
> byt-nuc          total:199  pass:158  dwarn:0   dfail:0   fail:0   skip:41
> hsw-brixbox      total:200  pass:174  dwarn:0   dfail:0   fail:0   skip:26
> hsw-gt2          total:200  pass:178  dwarn:0   dfail:0   fail:1   skip:21
> ilk-hp8440p      total:200  pass:139  dwarn:0   dfail:0   fail:0   skip:61
> ivb-t430s        total:200  pass:168  dwarn:0   dfail:0   fail:0   skip:32
> skl-i7k-2        total:200  pass:173  dwarn:0   dfail:0   fail:0   skip:27
> skl-nuci5        total:200  pass:189  dwarn:0   dfail:0   fail:0   skip:11
> snb-dellxps      total:200  pass:158  dwarn:0   dfail:0   fail:0   skip:42
> snb-x220t        total:200  pass:158  dwarn:0   dfail:0   fail:1   skip:41
>
> Results at /archive/results/CI_IGT_test/Patchwork_2068/
>
> f814551aa7232ed36d71244dd148b48660b53a78 drm-intel-nightly: 2016y-04m-25d-11h-36m-27s UTC integration manifest
> c8a3953 drm/i915: resize the GuC WOPCM for rc6
>
>

--
    Peter Antoine (Android Graphics Driver Software Engineer)
    ---------------------------------------------------------------------
    Intel Corporation (UK) Limited
    Registered No. 1134945 (England)
    Registered Office: Pipers Way, Swindon SN3 1RJ
    VAT No: 860 2173 47
Daniel Vetter April 26, 2016, 2:20 p.m. UTC | #2 
On Tue, Apr 26, 2016 at 11:38:46AM +0100, Peter Antoine wrote:
> On Tue, 26 Apr 2016, Patchwork wrote:
> 
> >== Series Details ==
> >
> >Series: drm/i915: resize the GuC WOPCM for rc6
> >URL   : https://patchwork.freedesktop.org/series/6313/
> >State : failure
> >
> >== Summary ==
> >
> >Series 6313v1 drm/i915: resize the GuC WOPCM for rc6
> >http://patchwork.freedesktop.org/api/1.0/series/6313/revisions/1/mbox/
> >
> >Test kms_flip:
> >       Subgroup basic-flip-vs-wf_vblank:
> >               pass       -> FAIL       (hsw-gt2)
> Patch cannot effect HSW as platform does not have GuC and GuC code is all
> guarded by platform. False Failure.
> 
> >Test kms_force_connector_basic:
> >       Subgroup force-edid:
> >               pass       -> SKIP       (ivb-t430s)
> Nothing to do with display.
> 
> >Test kms_pipe_crc_basic:
> >       Subgroup read-crc-pipe-b-frame-sequence:
> >               skip       -> PASS       (bdw-nuci7)
> Same.

The idea is to digg through bugzilla to make sure we have bugs for all of
these, not just shrug them off.

Yes this is work, and yes it's meant to motivate people to fix up all the
fail we still have.
-Daniel

> 
> >
> >bdw-nuci7        total:200  pass:188  dwarn:0   dfail:0   fail:0   skip:12
> >bdw-ultra        total:200  pass:175  dwarn:0   dfail:0   fail:0   skip:25
> >bsw-nuc-2        total:199  pass:158  dwarn:0   dfail:0   fail:0   skip:41
> >byt-nuc          total:199  pass:158  dwarn:0   dfail:0   fail:0   skip:41
> >hsw-brixbox      total:200  pass:174  dwarn:0   dfail:0   fail:0   skip:26
> >hsw-gt2          total:200  pass:178  dwarn:0   dfail:0   fail:1   skip:21
> >ilk-hp8440p      total:200  pass:139  dwarn:0   dfail:0   fail:0   skip:61
> >ivb-t430s        total:200  pass:168  dwarn:0   dfail:0   fail:0   skip:32
> >skl-i7k-2        total:200  pass:173  dwarn:0   dfail:0   fail:0   skip:27
> >skl-nuci5        total:200  pass:189  dwarn:0   dfail:0   fail:0   skip:11
> >snb-dellxps      total:200  pass:158  dwarn:0   dfail:0   fail:0   skip:42
> >snb-x220t        total:200  pass:158  dwarn:0   dfail:0   fail:1   skip:41
> >
> >Results at /archive/results/CI_IGT_test/Patchwork_2068/
> >
> >f814551aa7232ed36d71244dd148b48660b53a78 drm-intel-nightly: 2016y-04m-25d-11h-36m-27s UTC integration manifest
> >c8a3953 drm/i915: resize the GuC WOPCM for rc6
> >
> >
> 
> --
>    Peter Antoine (Android Graphics Driver Software Engineer)
>    ---------------------------------------------------------------------
>    Intel Corporation (UK) Limited
>    Registered No. 1134945 (England)
>    Registered Office: Pipers Way, Swindon SN3 1RJ
>    VAT No: 860 2173 47
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Paauwe, Bob J May 10, 2016, 3:59 p.m. UTC | #3 
On Tue, 26 Apr 2016 10:11:41 +0100
Peter Antoine <peter.antoine@intel.com> wrote:

> This patch resizes the GuC WOPCM to so that the GuC and the RC6 memory
> spaces do not overlap.

Hi Peter,

With this patch applied to our IOTG kernel tree, I see a regression
with the RC6 residency values.  The pm_rc6_residency fails the accuracy
test. 

The counter is still updating, but instead of seeing appx. 3000ms in
RC6 I see appx. 100ms during the 3 second sleep.

Simply reverting this one change makes the RC6 residency counts go back
to normal.  Seems like this patch should fix a problem like this, not
cause it. 

This is on a Leaf Hill BXT CRB platform.

Any pointers or thoughts on how to debug this would be appreciated.

Thanks,
Bob

> 
> Issue: https://jira01.devtools.intel.com/browse/VIZ-6638
> Signed-off-by: Peter Antoine <peter.antoine@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_guc_reg.h     | 5 +++--
>  drivers/gpu/drm/i915/intel_guc_loader.c | 6 +++++-
>  2 files changed, 8 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_guc_reg.h b/drivers/gpu/drm/i915/i915_guc_reg.h
> index 80786d9..6e01238 100644
> --- a/drivers/gpu/drm/i915/i915_guc_reg.h
> +++ b/drivers/gpu/drm/i915/i915_guc_reg.h
> @@ -68,10 +68,11 @@
>  #define GUC_MAX_IDLE_COUNT		_MMIO(0xC3E4)
>  
>  #define GUC_WOPCM_SIZE			_MMIO(0xc050)
> -#define   GUC_WOPCM_SIZE_VALUE  	  (0x80 << 12)	/* 512KB */
> +#define   GUC_WOPCM_SIZE_VALUE		(0x80 << 12)	/* 512KB */
> +#define   BXT_GUC_WOPCM_SIZE_VALUE	(0x70 << 12)	/* 448KB */
>  
>  /* GuC addresses below GUC_WOPCM_TOP don't map through the GTT */
> -#define	GUC_WOPCM_TOP			(GUC_WOPCM_SIZE_VALUE)
> +#define	GUC_WOPCM_TOP			(0x80 << 12)	/* 512KB */
>  
>  #define GEN8_GT_PM_CONFIG		_MMIO(0x138140)
>  #define GEN9LP_GT_PM_CONFIG		_MMIO(0x138140)
> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
> index fc3ff68..38fb321 100644
> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
> @@ -312,7 +312,11 @@ static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
>  	intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
>  
>  	/* init WOPCM */
> -	I915_WRITE(GUC_WOPCM_SIZE, GUC_WOPCM_SIZE_VALUE);
> +	if (IS_BROXTON(dev))
> +		I915_WRITE(GUC_WOPCM_SIZE, BXT_GUC_WOPCM_SIZE_VALUE);
> +	else
> +		I915_WRITE(GUC_WOPCM_SIZE, GUC_WOPCM_SIZE_VALUE);
> +
>  	I915_WRITE(DMA_GUC_WOPCM_OFFSET, GUC_WOPCM_OFFSET_VALUE);
>  
>  	/* Enable MIA caching. GuC clock gating is disabled. */
Peter Antoine May 10, 2016, 6:46 p.m. UTC | #4 
Hi Bob,

It was tested on a BXT-T RVP and LeafHill A and worked fine. The patch has been in the Android tree for at least a couple of months (probably more) and has seemed to be stable. But, not sure Android was run on the BXT CRB.
 
It could be the GuC firmware crashing, there are some fixes in 8.7. Has the size of the SRAM changed on that board?
Is something else reserving space in that area?

The size that was reserved was passed onto us from the GuC firmware team via the RC6 team. It might be worth talking to the power team in Bangalore. sagar.a.kamble@intel.com is probably your best bet for RC6 issues.

I hope that helps.

Peter. 

-----Original Message-----
From: Paauwe, Bob J 
Sent: Tuesday, May 10, 2016 4:59 PM
To: Antoine, Peter <peter.antoine@intel.com>
Cc: intel-gfx@lists.freedesktop.org; Vivi, Rodrigo <rodrigo.vivi@intel.com>
Subject: Re: [Intel-gfx] [PATCH v3] drm/i915: resize the GuC WOPCM for rc6

On Tue, 26 Apr 2016 10:11:41 +0100
Peter Antoine <peter.antoine@intel.com> wrote:

> This patch resizes the GuC WOPCM to so that the GuC and the RC6 memory 
> spaces do not overlap.

Hi Peter,

With this patch applied to our IOTG kernel tree, I see a regression with the RC6 residency values.  The pm_rc6_residency fails the accuracy test. 

The counter is still updating, but instead of seeing appx. 3000ms in
RC6 I see appx. 100ms during the 3 second sleep.

Simply reverting this one change makes the RC6 residency counts go back to normal.  Seems like this patch should fix a problem like this, not cause it. 

This is on a Leaf Hill BXT CRB platform.

Any pointers or thoughts on how to debug this would be appreciated.

Thanks,
Bob

> 
> Issue: https://jira01.devtools.intel.com/browse/VIZ-6638
> Signed-off-by: Peter Antoine <peter.antoine@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_guc_reg.h     | 5 +++--
>  drivers/gpu/drm/i915/intel_guc_loader.c | 6 +++++-
>  2 files changed, 8 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_guc_reg.h 
> b/drivers/gpu/drm/i915/i915_guc_reg.h
> index 80786d9..6e01238 100644
> --- a/drivers/gpu/drm/i915/i915_guc_reg.h
> +++ b/drivers/gpu/drm/i915/i915_guc_reg.h
> @@ -68,10 +68,11 @@
>  #define GUC_MAX_IDLE_COUNT		_MMIO(0xC3E4)
>  
>  #define GUC_WOPCM_SIZE			_MMIO(0xc050)
> -#define   GUC_WOPCM_SIZE_VALUE  	  (0x80 << 12)	/* 512KB */
> +#define   GUC_WOPCM_SIZE_VALUE		(0x80 << 12)	/* 512KB */
> +#define   BXT_GUC_WOPCM_SIZE_VALUE	(0x70 << 12)	/* 448KB */
>  
>  /* GuC addresses below GUC_WOPCM_TOP don't map through the GTT */
> -#define	GUC_WOPCM_TOP			(GUC_WOPCM_SIZE_VALUE)
> +#define	GUC_WOPCM_TOP			(0x80 << 12)	/* 512KB */
>  
>  #define GEN8_GT_PM_CONFIG		_MMIO(0x138140)
>  #define GEN9LP_GT_PM_CONFIG		_MMIO(0x138140)
> diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c 
> b/drivers/gpu/drm/i915/intel_guc_loader.c
> index fc3ff68..38fb321 100644
> --- a/drivers/gpu/drm/i915/intel_guc_loader.c
> +++ b/drivers/gpu/drm/i915/intel_guc_loader.c
> @@ -312,7 +312,11 @@ static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
>  	intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
>  
>  	/* init WOPCM */
> -	I915_WRITE(GUC_WOPCM_SIZE, GUC_WOPCM_SIZE_VALUE);
> +	if (IS_BROXTON(dev))
> +		I915_WRITE(GUC_WOPCM_SIZE, BXT_GUC_WOPCM_SIZE_VALUE);
> +	else
> +		I915_WRITE(GUC_WOPCM_SIZE, GUC_WOPCM_SIZE_VALUE);
> +
>  	I915_WRITE(DMA_GUC_WOPCM_OFFSET, GUC_WOPCM_OFFSET_VALUE);
>  
>  	/* Enable MIA caching. GuC clock gating is disabled. */



--
--
Bob Paauwe                  
Bob.J.Paauwe@intel.com
IOTG / PED Software Organization
Intel Corp.  Folsom, CA
(916) 356-6193
Peter Antoine May 12, 2016, 4:29 p.m. UTC | #5 
-----Original Message-----
From: Daniel Vetter [mailto:daniel.vetter@ffwll.ch] On Behalf Of Daniel Vetter

Sent: Tuesday, April 26, 2016 3:20 PM
To: Antoine, Peter <peter.antoine@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] ? Fi.CI.BAT: failure for drm/i915: resize the GuC WOPCM for rc6

On Tue, Apr 26, 2016 at 11:38:46AM +0100, Peter Antoine wrote:
> On Tue, 26 Apr 2016, Patchwork wrote:

> 

> >== Series Details ==

> >

> >Series: drm/i915: resize the GuC WOPCM for rc6

> >URL   : https://patchwork.freedesktop.org/series/6313/

> >State : failure

> >

> >== Summary ==

> >

> >Series 6313v1 drm/i915: resize the GuC WOPCM for rc6 

> >http://patchwork.freedesktop.org/api/1.0/series/6313/revisions/1/mbox

> >/

> >

> >Test kms_flip:

> >       Subgroup basic-flip-vs-wf_vblank:

> >               pass       -> FAIL       (hsw-gt2)

> Patch cannot effect HSW as platform does not have GuC and GuC code is 

> all guarded by platform. False Failure.


Already reported.
https://bugs.freedesktop.org/show_bug.cgi?id=94294

> 

> >Test kms_force_connector_basic:

> >       Subgroup force-edid:

> >               pass       -> SKIP       (ivb-t430s)

> Nothing to do with display.


Already reported:
https://bugs.freedesktop.org/show_bug.cgi?id=93123
> 

> >Test kms_pipe_crc_basic:

> >       Subgroup read-crc-pipe-b-frame-sequence:

> >               skip       -> PASS       (bdw-nuci7)

> Same.

The BAT should not fail on a pass.

The idea is to digg through bugzilla to make sure we have bugs for all of these, not just shrug them off.

Yes this is work, and yes it's meant to motivate people to fix up all the fail we still have.
-Daniel

> 

> >

> >bdw-nuci7        total:200  pass:188  dwarn:0   dfail:0   fail:0   skip:12

> >bdw-ultra        total:200  pass:175  dwarn:0   dfail:0   fail:0   skip:25

> >bsw-nuc-2        total:199  pass:158  dwarn:0   dfail:0   fail:0   skip:41

> >byt-nuc          total:199  pass:158  dwarn:0   dfail:0   fail:0   skip:41

> >hsw-brixbox      total:200  pass:174  dwarn:0   dfail:0   fail:0   skip:26

> >hsw-gt2          total:200  pass:178  dwarn:0   dfail:0   fail:1   skip:21

> >ilk-hp8440p      total:200  pass:139  dwarn:0   dfail:0   fail:0   skip:61

> >ivb-t430s        total:200  pass:168  dwarn:0   dfail:0   fail:0   skip:32

> >skl-i7k-2        total:200  pass:173  dwarn:0   dfail:0   fail:0   skip:27

> >skl-nuci5        total:200  pass:189  dwarn:0   dfail:0   fail:0   skip:11

> >snb-dellxps      total:200  pass:158  dwarn:0   dfail:0   fail:0   skip:42

> >snb-x220t        total:200  pass:158  dwarn:0   dfail:0   fail:1   skip:41

> >

> >Results at /archive/results/CI_IGT_test/Patchwork_2068/

> >

> >f814551aa7232ed36d71244dd148b48660b53a78 drm-intel-nightly: 

> >2016y-04m-25d-11h-36m-27s UTC integration manifest

> >c8a3953 drm/i915: resize the GuC WOPCM for rc6

> >

> >

> 

> --

>    Peter Antoine (Android Graphics Driver Software Engineer)

>    ---------------------------------------------------------------------

>    Intel Corporation (UK) Limited

>    Registered No. 1134945 (England)

>    Registered Office: Pipers Way, Swindon SN3 1RJ

>    VAT No: 860 2173 47

> _______________________________________________

> Intel-gfx mailing list

> Intel-gfx@lists.freedesktop.org

> https://lists.freedesktop.org/mailman/listinfo/intel-gfx


--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/i915_guc_reg.h b/drivers/gpu/drm/i915/i915_guc_reg.h
index 80786d9..6e01238 100644
--- a/drivers/gpu/drm/i915/i915_guc_reg.h
+++ b/drivers/gpu/drm/i915/i915_guc_reg.h
@@ -68,10 +68,11 @@ 
 #define GUC_MAX_IDLE_COUNT		_MMIO(0xC3E4)
 
 #define GUC_WOPCM_SIZE			_MMIO(0xc050)
-#define   GUC_WOPCM_SIZE_VALUE  	  (0x80 << 12)	/* 512KB */
+#define   GUC_WOPCM_SIZE_VALUE		(0x80 << 12)	/* 512KB */
+#define   BXT_GUC_WOPCM_SIZE_VALUE	(0x70 << 12)	/* 448KB */
 
 /* GuC addresses below GUC_WOPCM_TOP don't map through the GTT */
-#define	GUC_WOPCM_TOP			(GUC_WOPCM_SIZE_VALUE)
+#define	GUC_WOPCM_TOP			(0x80 << 12)	/* 512KB */
 
 #define GEN8_GT_PM_CONFIG		_MMIO(0x138140)
 #define GEN9LP_GT_PM_CONFIG		_MMIO(0x138140)
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index fc3ff68..38fb321 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -312,7 +312,11 @@  static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
 	intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
 
 	/* init WOPCM */
-	I915_WRITE(GUC_WOPCM_SIZE, GUC_WOPCM_SIZE_VALUE);
+	if (IS_BROXTON(dev))
+		I915_WRITE(GUC_WOPCM_SIZE, BXT_GUC_WOPCM_SIZE_VALUE);
+	else
+		I915_WRITE(GUC_WOPCM_SIZE, GUC_WOPCM_SIZE_VALUE);
+
 	I915_WRITE(DMA_GUC_WOPCM_OFFSET, GUC_WOPCM_OFFSET_VALUE);
 
 	/* Enable MIA caching. GuC clock gating is disabled. */