| Message ID | 1464562768-8954-4-git-send-email-peer.adelt@c-lab.de (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 05/30/2016 12:59 AM, peer.adelt@c-lab.de wrote: > From: Peer Adelt <peer.adelt@c-lab.de> > > Puts the content of data register D[a] into E[c][63:32] and the > content of data register D[b] into E[c][31:0]. > > Signed-off-by: Peer Adelt <peer.adelt@c-lab.de> > --- > target-tricore/translate.c | 4 ++++ > target-tricore/tricore-opcodes.h | 1 + > 2 files changed, 5 insertions(+) > > diff --git a/target-tricore/translate.c b/target-tricore/translate.c > index e66b433..2145f64 100644 > --- a/target-tricore/translate.c > +++ b/target-tricore/translate.c > @@ -6224,6 +6224,10 @@ static void decode_rr_accumulator(CPUTriCoreState *env, DisasContext *ctx) > case OPC2_32_RR_MOV: > tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]); > break; > + case OPC2_32_RR_MOV_EXT: > + tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]); > + tcg_gen_mov_tl(cpu_gpr_d[(r3 + 1)], cpu_gpr_d[r2]); > + break; Since this is a 1.6+ instruction, please check the hflags for the 1.6 ISA and raise an exception if 1.6+ ISA is not met. See OPC1_16_SRC_MOV_E as an example. Cheers, Bastian
On 05/29/2016 03:59 PM, peer.adelt@c-lab.de wrote: > + tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]); > + tcg_gen_mov_tl(cpu_gpr_d[(r3 + 1)], cpu_gpr_d[r2]); Don't add pointless parenthesis. But more importantly, you need to worry about overlap between r3 and r2. In the general case you'll need a temporary to perform this move. r~
diff --git a/target-tricore/translate.c b/target-tricore/translate.c index e66b433..2145f64 100644 --- a/target-tricore/translate.c +++ b/target-tricore/translate.c @@ -6224,6 +6224,10 @@ static void decode_rr_accumulator(CPUTriCoreState *env, DisasContext *ctx) case OPC2_32_RR_MOV: tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]); break; + case OPC2_32_RR_MOV_EXT: + tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]); + tcg_gen_mov_tl(cpu_gpr_d[(r3 + 1)], cpu_gpr_d[r2]); + break; case OPC2_32_RR_NE: tcg_gen_setcond_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); diff --git a/target-tricore/tricore-opcodes.h b/target-tricore/tricore-opcodes.h index df666b0..2f25613 100644 --- a/target-tricore/tricore-opcodes.h +++ b/target-tricore/tricore-opcodes.h @@ -1062,6 +1062,7 @@ enum { OPC2_32_RR_MIN_H = 0x78, OPC2_32_RR_MIN_HU = 0x79, OPC2_32_RR_MOV = 0x1f, + OPC2_32_RR_MOV_EXT = 0x81, OPC2_32_RR_NE = 0x11, OPC2_32_RR_OR_EQ = 0x27, OPC2_32_RR_OR_GE = 0x2b,