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[RFC,v2,09/13] tcg/sparc: Add support for fence

Message ID 20160531183928.29406-10-bobby.prani@gmail.com (mailing list archive)
State New, archived
Headers show

Commit Message

Pranith Kumar May 31, 2016, 6:39 p.m. UTC 
Cc: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Pranith Kumar <bobby.prani@gmail.com>
---
 tcg/sparc/tcg-target.inc.c | 8 ++++++++
 1 file changed, 8 insertions(+)

Comments

Richard Henderson May 31, 2016, 8:45 p.m. UTC | #1 
On 05/31/2016 11:39 AM, Pranith Kumar wrote:
> +    case INDEX_op_mb:
> +        /* membar #LoadLoad|#LoadStore|#StoreStore|#StoreLoad */
> +        tcg_out32(s, MEMBAR | 15);
> +        break;

With the argument, this needs to be

	if (a0 == TCG_MB_WRITE) {
		/* #StoreStore | #StoreLoad */
		a0 = 0xa;
	} else if (a0 == TCG_MB_READ) {
		/* #LoadStore | #LoadLoad */
		a0 = 0x5;
	} else {
		/* #StoreStore | #LoadStore | #StoreLoad | #LoadLoad */
		a0 = 0xf;
	}
	tcg_out32(s, MEMBAR | a0);


r~
diff mbox

Patch

diff --git a/tcg/sparc/tcg-target.inc.c b/tcg/sparc/tcg-target.inc.c
index a611885..81f263f 100644
--- a/tcg/sparc/tcg-target.inc.c
+++ b/tcg/sparc/tcg-target.inc.c
@@ -249,6 +249,8 @@  static const int tcg_target_call_oarg_regs[] = {
 #define STWA       (INSN_OP(3) | INSN_OP3(0x14))
 #define STXA       (INSN_OP(3) | INSN_OP3(0x1e))
 
+#define MEMBAR     (INSN_OP(2) | INSN_OP3(0x28) | INSN_RS1(15) | (1 << 13))
+
 #ifndef ASI_PRIMARY_LITTLE
 #define ASI_PRIMARY_LITTLE 0x88
 #endif
@@ -1450,6 +1452,11 @@  static void tcg_out_op(TCGContext *s, TCGOpcode opc,
 	tcg_out_arithc(s, a0, TCG_REG_G0, a1, const_args[1], c);
 	break;
 
+    case INDEX_op_mb:
+        /* membar #LoadLoad|#LoadStore|#StoreStore|#StoreLoad */
+        tcg_out32(s, MEMBAR | 15);
+        break;
+
     case INDEX_op_mov_i32:  /* Always emitted via tcg_out_mov.  */
     case INDEX_op_mov_i64:
     case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi.  */
@@ -1551,6 +1558,7 @@  static const TCGTargetOpDef sparc_op_defs[] = {
     { INDEX_op_qemu_st_i32, { "sZ", "A" } },
     { INDEX_op_qemu_st_i64, { "SZ", "A" } },
 
+    { INDEX_op_mb, { "r" } },
     { -1 },
 };