| Message ID | 1464966911-18949-2-git-send-email-zyw@rock-chips.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Fri, Jun 03, 2016 at 11:15:08PM +0800, Chris Zhong wrote: > This patch adds a binding that describes the Rockchip USB Type-C PHY > for rk3399 > > Signed-off-by: Chris Zhong <zyw@rock-chips.com> > > --- > > Changes in v1: > - add extcon node description > - move the registers in phy driver > - remove the suffix of reset > > .../devicetree/bindings/phy/phy-rockchip-typec.txt | 46 ++++++++++++++++++++++ > 1 file changed, 46 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt > > diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt b/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt > new file mode 100644 > index 0000000..964e0f7 > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt > @@ -0,0 +1,46 @@ > +* ROCKCHIP type-c PHY > +--------------------- > + > +Required properties: > + - compatible: should be "rockchip,rk3399-typec-phy0" or > + "rockchip,rk3399-typec-phy1" What's the difference between 0 and 1? If it is to handle the register offsets you have in the previous version and the phy blocks are identical, then the compatible strings should be the same. > + - reg : Address and length of the usb phy control register set > + - rockchip,grf : phandle to the syscon managing the "general > + register files" > + - clocks : phandle + clock specifier for the phy clocks > + - clock-names: string, clock name, must be "tcpdcore", "tcpdphy_ref"; > + - resets : a list of phandle + reset specifier pairs > + - reset-names : string reset name, must be: > + "tcphy", "tcphy_pipe", "uphy_tcphy" > + - #phy-cells: Must be 0. See ./phy-bindings.txt for details. > + - extcon: extcon specifier for the Power Delivery
Hi Rob On 06/06/2016 10:27 PM, Rob Herring wrote: > On Fri, Jun 03, 2016 at 11:15:08PM +0800, Chris Zhong wrote: >> This patch adds a binding that describes the Rockchip USB Type-C PHY >> for rk3399 >> >> Signed-off-by: Chris Zhong <zyw@rock-chips.com> >> >> --- >> >> Changes in v1: >> - add extcon node description >> - move the registers in phy driver >> - remove the suffix of reset >> >> .../devicetree/bindings/phy/phy-rockchip-typec.txt | 46 ++++++++++++++++++++++ >> 1 file changed, 46 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt >> >> diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt b/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt >> new file mode 100644 >> index 0000000..964e0f7 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt >> @@ -0,0 +1,46 @@ >> +* ROCKCHIP type-c PHY >> +--------------------- >> + >> +Required properties: >> + - compatible: should be "rockchip,rk3399-typec-phy0" or >> + "rockchip,rk3399-typec-phy1" > What's the difference between 0 and 1? If it is to handle the register > offsets you have in the previous version and the phy blocks are > identical, then the compatible strings should be the same. yes, the registers are different between 0 and 1, and there is a grf register(0x6268) for switch the phy 0 and phy 1 > >> + - reg : Address and length of the usb phy control register set >> + - rockchip,grf : phandle to the syscon managing the "general >> + register files" >> + - clocks : phandle + clock specifier for the phy clocks >> + - clock-names: string, clock name, must be "tcpdcore", "tcpdphy_ref"; >> + - resets : a list of phandle + reset specifier pairs >> + - reset-names : string reset name, must be: >> + "tcphy", "tcphy_pipe", "uphy_tcphy" >> + - #phy-cells: Must be 0. See ./phy-bindings.txt for details. >> + - extcon: extcon specifier for the Power Delivery > >
On Mon, Jun 6, 2016 at 7:33 PM, Chris Zhong <zyw@rock-chips.com> wrote: > Hi Rob > > > On 06/06/2016 10:27 PM, Rob Herring wrote: >> >> On Fri, Jun 03, 2016 at 11:15:08PM +0800, Chris Zhong wrote: >>> >>> This patch adds a binding that describes the Rockchip USB Type-C PHY >>> for rk3399 >>> >>> Signed-off-by: Chris Zhong <zyw@rock-chips.com> >>> >>> --- >>> >>> Changes in v1: >>> - add extcon node description >>> - move the registers in phy driver >>> - remove the suffix of reset >>> >>> .../devicetree/bindings/phy/phy-rockchip-typec.txt | 46 >>> ++++++++++++++++++++++ >>> 1 file changed, 46 insertions(+) >>> create mode 100644 >>> Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt >>> >>> diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt >>> b/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt >>> new file mode 100644 >>> index 0000000..964e0f7 >>> --- /dev/null >>> +++ b/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt >>> @@ -0,0 +1,46 @@ >>> +* ROCKCHIP type-c PHY >>> +--------------------- >>> + >>> +Required properties: >>> + - compatible: should be "rockchip,rk3399-typec-phy0" or >>> + "rockchip,rk3399-typec-phy1" >> >> What's the difference between 0 and 1? If it is to handle the register >> offsets you have in the previous version and the phy blocks are >> identical, then the compatible strings should be the same. > > yes, the registers are different between 0 and 1, and there is a grf > register(0x6268) for switch the phy 0 and phy 1 But GRF is in a separate block and not part of the phy, right? Rob
Hi Rob On 06/07/2016 09:46 PM, Rob Herring wrote: > On Mon, Jun 6, 2016 at 7:33 PM, Chris Zhong <zyw@rock-chips.com> wrote: >> Hi Rob >> >> >> On 06/06/2016 10:27 PM, Rob Herring wrote: >>> On Fri, Jun 03, 2016 at 11:15:08PM +0800, Chris Zhong wrote: >>>> This patch adds a binding that describes the Rockchip USB Type-C PHY >>>> for rk3399 >>>> >>>> Signed-off-by: Chris Zhong <zyw@rock-chips.com> >>>> >>>> --- >>>> >>>> Changes in v1: >>>> - add extcon node description >>>> - move the registers in phy driver >>>> - remove the suffix of reset >>>> >>>> .../devicetree/bindings/phy/phy-rockchip-typec.txt | 46 >>>> ++++++++++++++++++++++ >>>> 1 file changed, 46 insertions(+) >>>> create mode 100644 >>>> Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt >>>> >>>> diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt >>>> b/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt >>>> new file mode 100644 >>>> index 0000000..964e0f7 >>>> --- /dev/null >>>> +++ b/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt >>>> @@ -0,0 +1,46 @@ >>>> +* ROCKCHIP type-c PHY >>>> +--------------------- >>>> + >>>> +Required properties: >>>> + - compatible: should be "rockchip,rk3399-typec-phy0" or >>>> + "rockchip,rk3399-typec-phy1" >>> What's the difference between 0 and 1? If it is to handle the register >>> offsets you have in the previous version and the phy blocks are >>> identical, then the compatible strings should be the same. >> yes, the registers are different between 0 and 1, and there is a grf >> register(0x6268) for switch the phy 0 and phy 1 > But GRF is in a separate block and not part of the phy, right? > > Rob The GRF is not a single function block, it contain many registers to control other block. For Type-c phy, the type-c orientation, phy select, and some phy status registers are embedded in GRF So the GRF is registered for a syscon driver, the phy driver call regmap to access the registers. > > >
On Wed, Jun 08, 2016 at 09:38:33AM +0800, Chris Zhong wrote: > Hi Rob > > On 06/07/2016 09:46 PM, Rob Herring wrote: > >On Mon, Jun 6, 2016 at 7:33 PM, Chris Zhong <zyw@rock-chips.com> wrote: > >>Hi Rob > >> > >> > >>On 06/06/2016 10:27 PM, Rob Herring wrote: > >>>On Fri, Jun 03, 2016 at 11:15:08PM +0800, Chris Zhong wrote: > >>>>This patch adds a binding that describes the Rockchip USB Type-C PHY > >>>>for rk3399 > >>>> > >>>>Signed-off-by: Chris Zhong <zyw@rock-chips.com> > >>>> > >>>>--- > >>>> > >>>>Changes in v1: > >>>>- add extcon node description > >>>>- move the registers in phy driver > >>>>- remove the suffix of reset > >>>> > >>>> .../devicetree/bindings/phy/phy-rockchip-typec.txt | 46 > >>>>++++++++++++++++++++++ > >>>> 1 file changed, 46 insertions(+) > >>>> create mode 100644 > >>>>Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt > >>>> > >>>>diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt > >>>>b/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt > >>>>new file mode 100644 > >>>>index 0000000..964e0f7 > >>>>--- /dev/null > >>>>+++ b/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt > >>>>@@ -0,0 +1,46 @@ > >>>>+* ROCKCHIP type-c PHY > >>>>+--------------------- > >>>>+ > >>>>+Required properties: > >>>>+ - compatible: should be "rockchip,rk3399-typec-phy0" or > >>>>+ "rockchip,rk3399-typec-phy1" > >>>What's the difference between 0 and 1? If it is to handle the register > >>>offsets you have in the previous version and the phy blocks are > >>>identical, then the compatible strings should be the same. > >>yes, the registers are different between 0 and 1, and there is a grf > >>register(0x6268) for switch the phy 0 and phy 1 > >But GRF is in a separate block and not part of the phy, right? > > > >Rob > The GRF is not a single function block, it contain many registers to control > other block. > For Type-c phy, the type-c orientation, phy select, and some phy status > registers are embedded in GRF > So the GRF is registered for a syscon driver, the phy driver call regmap to > access the registers. Right, so different compatible strings is wrong here. Keep it more like you had it before. Rob
diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt b/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt new file mode 100644 index 0000000..964e0f7 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt @@ -0,0 +1,46 @@ +* ROCKCHIP type-c PHY +--------------------- + +Required properties: + - compatible: should be "rockchip,rk3399-typec-phy0" or + "rockchip,rk3399-typec-phy1" + - reg : Address and length of the usb phy control register set + - rockchip,grf : phandle to the syscon managing the "general + register files" + - clocks : phandle + clock specifier for the phy clocks + - clock-names: string, clock name, must be "tcpdcore", "tcpdphy_ref"; + - resets : a list of phandle + reset specifier pairs + - reset-names : string reset name, must be: + "tcphy", "tcphy_pipe", "uphy_tcphy" + - #phy-cells: Must be 0. See ./phy-bindings.txt for details. + - extcon: extcon specifier for the Power Delivery + +Example: + tcphy0: phy@ff7c0000 { + compatible = "rockchip,rk3399-typec-phy0"; + reg = <0x0 0xff7c0000 0x0 0x40000>; + #phy-cells = <0>; + extcon = <&fusb1>; + rockchip,grf = <&grf>; + clocks = <&cru SCLK_UPHY0_TCPDCORE>, + <&cru SCLK_UPHY0_TCPDPHY_REF>; + clock-names = "tcpdcore", "tcpdphy_ref"; + resets = <&cru SRST_UPHY0>, + <&cru SRST_UPHY0_PIPE_L00>, + <&cru SRST_P_UPHY0_TCPHY>; + reset-names = "tcphy", "tcphy_pipe", "uphy_tcphy"; + }; + + tcphy1: phy@ff800000 { + compatible = "rockchip,rk3399-typec-phy1"; + reg = <0x0 0xff800000 0x0 0x40000>; + #phy-cells = <0>; + rockchip,grf = <&grf>; + clocks = <&cru SCLK_UPHY1_TCPDCORE>, + <&cru SCLK_UPHY1_TCPDPHY_REF>; + clock-names = "tcpdcore", "tcpdphy_ref"; + resets = <&cru SRST_UPHY1>, + <&cru SRST_UPHY1_PIPE_L00>, + <&cru SRST_P_UPHY1_TCPHY>; + reset-names = "tcphy", "tcphy_pipe", "uphy_tcphy"; + };
This patch adds a binding that describes the Rockchip USB Type-C PHY for rk3399 Signed-off-by: Chris Zhong <zyw@rock-chips.com> --- Changes in v1: - add extcon node description - move the registers in phy driver - remove the suffix of reset .../devicetree/bindings/phy/phy-rockchip-typec.txt | 46 ++++++++++++++++++++++ 1 file changed, 46 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt