| Message ID | 1465235791-7064-3-git-send-email-marc.zyngier@arm.com (mailing list archive) |
|---|---|
| State | Not Applicable |
| Headers | show |
On 06/06/2016 07:56 PM, Marc Zyngier wrote: > The ARM architected timer specification mandates that the interrupt > associated with each timer is level triggered (which corresponds to > the "counter >= comparator" condition). > > A number of DTs are being remarkably creative, declaring the interrupt > to be edge triggered. A quick look at the TRM for the corresponding ARM > CPUs clearly shows that this is wrong, and I've corrected those. > For non-ARM designs (and in the absence of a publicly available TRM), > I've made them active low as well, which can't be completely wrong > as the GIC cannot disinguish between level low and level high. > > The respective maintainers are of course welcome to prove me wrong. > > While I was at it, I took the liberty to fix a couple of related issue, > such as some spurious affinity bits on ThunderX, and their complete > absence on ls1043a (both of which seem to be related to copy-pasting > from other DTs). > > Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> > --- > arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 8 ++++---- > arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 8 ++++---- > arch/arm64/boot/dts/apm/apm-storm.dtsi | 8 ++++---- > arch/arm64/boot/dts/broadcom/ns2.dtsi | 8 ++++---- > arch/arm64/boot/dts/cavium/thunder-88xx.dtsi | 8 ++++---- > arch/arm64/boot/dts/exynos/exynos7.dtsi | 8 ++++---- > arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 8 ++++---- > arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 8 ++++---- > arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi | 8 ++++---- > arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 8 ++++---- > 10 files changed, 40 insertions(+), 40 deletions(-) > (...) > diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi > index ca663df..1628315 100644 > --- a/arch/arm64/boot/dts/exynos/exynos7.dtsi > +++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi > @@ -473,10 +473,10 @@ > > timer { > compatible = "arm,armv8-timer"; > - interrupts = <1 13 0xff01>, > - <1 14 0xff01>, > - <1 11 0xff01>, > - <1 10 0xff01>; > + interrupts = <1 13 0xff08>, > + <1 14 0xff08>, > + <1 11 0xff08>, > + <1 10 0xff08>; > }; > > pmu_system_controller: system-controller@105c0000 { Acked-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> I got a conflicting patch in my tree so it would be nice if your fix went to current release cycle: https://git.kernel.org/cgit/linux/kernel/git/krzk/linux.git/commit/?h=next/dt64&id=8b77005c40376816885b100bcd358887d29e323f Best regards, Krzysztof
On 6.6.2016 19:56, Marc Zyngier wrote: > The ARM architected timer specification mandates that the interrupt > associated with each timer is level triggered (which corresponds to > the "counter >= comparator" condition). > > A number of DTs are being remarkably creative, declaring the interrupt > to be edge triggered. A quick look at the TRM for the corresponding ARM > CPUs clearly shows that this is wrong, and I've corrected those. > For non-ARM designs (and in the absence of a publicly available TRM), > I've made them active low as well, which can't be completely wrong > as the GIC cannot disinguish between level low and level high. > > The respective maintainers are of course welcome to prove me wrong. > > While I was at it, I took the liberty to fix a couple of related issue, > such as some spurious affinity bits on ThunderX, and their complete > absence on ls1043a (both of which seem to be related to copy-pasting > from other DTs). > > Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> > --- > arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 8 ++++---- > arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 8 ++++---- > arch/arm64/boot/dts/apm/apm-storm.dtsi | 8 ++++---- > arch/arm64/boot/dts/broadcom/ns2.dtsi | 8 ++++---- > arch/arm64/boot/dts/cavium/thunder-88xx.dtsi | 8 ++++---- > arch/arm64/boot/dts/exynos/exynos7.dtsi | 8 ++++---- > arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 8 ++++---- > arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 8 ++++---- > arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi | 8 ++++---- > arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 8 ++++---- > 10 files changed, 40 insertions(+), 40 deletions(-) > > diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi > index 445aa67..c2b9bcb 100644 > --- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi > +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi > @@ -255,10 +255,10 @@ > /* Local timer */ > timer { > compatible = "arm,armv8-timer"; > - interrupts = <1 13 0xf01>, > - <1 14 0xf01>, > - <1 11 0xf01>, > - <1 10 0xf01>; > + interrupts = <1 13 0xf08>, > + <1 14 0xf08>, > + <1 11 0xf08>, > + <1 10 0xf08>; > }; > > timer0: timer0@ffc03000 { > diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi > index 832815d..4d9d144 100644 > --- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi > +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi > @@ -100,13 +100,13 @@ > timer { > compatible = "arm,armv8-timer"; > interrupts = <GIC_PPI 13 > - (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>, > + (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, > <GIC_PPI 14 > - (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>, > + (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, > <GIC_PPI 11 > - (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>, > + (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, > <GIC_PPI 10 > - (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>; > + (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; > }; > > xtal: xtal-clk { > diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi b/arch/arm64/boot/dts/apm/apm-storm.dtsi > index 5147d76..1c4193f 100644 > --- a/arch/arm64/boot/dts/apm/apm-storm.dtsi > +++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi > @@ -110,10 +110,10 @@ > > timer { > compatible = "arm,armv8-timer"; > - interrupts = <1 0 0xff01>, /* Secure Phys IRQ */ > - <1 13 0xff01>, /* Non-secure Phys IRQ */ > - <1 14 0xff01>, /* Virt IRQ */ > - <1 15 0xff01>; /* Hyp IRQ */ > + interrupts = <1 0 0xff08>, /* Secure Phys IRQ */ > + <1 13 0xff08>, /* Non-secure Phys IRQ */ > + <1 14 0xff08>, /* Virt IRQ */ > + <1 15 0xff08>; /* Hyp IRQ */ > clock-frequency = <50000000>; > }; > > diff --git a/arch/arm64/boot/dts/broadcom/ns2.dtsi b/arch/arm64/boot/dts/broadcom/ns2.dtsi > index ec68ec1..9c2d8a7 100644 > --- a/arch/arm64/boot/dts/broadcom/ns2.dtsi > +++ b/arch/arm64/boot/dts/broadcom/ns2.dtsi > @@ -88,13 +88,13 @@ > timer { > compatible = "arm,armv8-timer"; > interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xff) | > - IRQ_TYPE_EDGE_RISING)>, > + IRQ_TYPE_LEVEL_LOW)>, > <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xff) | > - IRQ_TYPE_EDGE_RISING)>, > + IRQ_TYPE_LEVEL_LOW)>, > <GIC_PPI 11 (GIC_CPU_MASK_RAW(0xff) | > - IRQ_TYPE_EDGE_RISING)>, > + IRQ_TYPE_LEVEL_LOW)>, > <GIC_PPI 10 (GIC_CPU_MASK_RAW(0xff) | > - IRQ_TYPE_EDGE_RISING)>; > + IRQ_TYPE_LEVEL_LOW)>; > }; > > pmu { > diff --git a/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi b/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi > index 2eb9b22..382d86f 100644 > --- a/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi > +++ b/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi > @@ -354,10 +354,10 @@ > > timer { > compatible = "arm,armv8-timer"; > - interrupts = <1 13 0xff01>, > - <1 14 0xff01>, > - <1 11 0xff01>, > - <1 10 0xff01>; > + interrupts = <1 13 8>, > + <1 14 8>, > + <1 11 8>, > + <1 10 8>; > }; > > pmu { > diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi > index ca663df..1628315 100644 > --- a/arch/arm64/boot/dts/exynos/exynos7.dtsi > +++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi > @@ -473,10 +473,10 @@ > > timer { > compatible = "arm,armv8-timer"; > - interrupts = <1 13 0xff01>, > - <1 14 0xff01>, > - <1 11 0xff01>, > - <1 10 0xff01>; > + interrupts = <1 13 0xff08>, > + <1 14 0xff08>, > + <1 11 0xff08>, > + <1 10 0xff08>; > }; > > pmu_system_controller: system-controller@105c0000 { > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi > index c277ba6..b92543d 100644 > --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi > +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi > @@ -111,10 +111,10 @@ > > timer { > compatible = "arm,armv8-timer"; > - interrupts = <1 13 0x1>, /* Physical Secure PPI */ > - <1 14 0x1>, /* Physical Non-Secure PPI */ > - <1 11 0x1>, /* Virtual PPI */ > - <1 10 0x1>; /* Hypervisor PPI */ > + interrupts = <1 13 0xf08>, /* Physical Secure PPI */ > + <1 14 0xf08>, /* Physical Non-Secure PPI */ > + <1 11 0xf08>, /* Virtual PPI */ > + <1 10 0xf08>; /* Hypervisor PPI */ > fsl,erratum-a008585; > }; > > diff --git a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi > index 20d256b..b1d6bb8 100644 > --- a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi > +++ b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi > @@ -122,10 +122,10 @@ > > timer { > compatible = "arm,armv8-timer"; > - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>, > - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>, > - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>, > - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; > + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; > }; > > odmi: odmi@300000 { > diff --git a/arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi > index 9532880..5a8e0f4 100644 > --- a/arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi > +++ b/arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi > @@ -127,10 +127,10 @@ > > timer { > compatible = "arm,armv8-timer"; > - interrupts = <1 13 0xf01>, > - <1 14 0xf01>, > - <1 11 0xf01>, > - <1 10 0xf01>; > + interrupts = <1 13 0xf08>, > + <1 14 0xf08>, > + <1 11 0xf08>, > + <1 10 0xf08>; > }; > > soc { > diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi > index e595f22..3e2e51f 100644 > --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi > +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi > @@ -65,10 +65,10 @@ > timer { > compatible = "arm,armv8-timer"; > interrupt-parent = <&gic>; > - interrupts = <1 13 0xf01>, > - <1 14 0xf01>, > - <1 11 0xf01>, > - <1 10 0xf01>; > + interrupts = <1 13 0xf08>, > + <1 14 0xf08>, > + <1 11 0xf08>, > + <1 10 0xf08>; > }; > > amba_apu { > Acked-by: Michal Simek <michal.simek@xilinx.com> # ZynqMP Thanks, Michal
On 06/06/2016 12:56 PM, Marc Zyngier wrote: > The ARM architected timer specification mandates that the interrupt > associated with each timer is level triggered (which corresponds to > the "counter >= comparator" condition). > > A number of DTs are being remarkably creative, declaring the interrupt > to be edge triggered. A quick look at the TRM for the corresponding ARM > CPUs clearly shows that this is wrong, and I've corrected those. > For non-ARM designs (and in the absence of a publicly available TRM), > I've made them active low as well, which can't be completely wrong > as the GIC cannot disinguish between level low and level high. > > The respective maintainers are of course welcome to prove me wrong. > > While I was at it, I took the liberty to fix a couple of related issue, > such as some spurious affinity bits on ThunderX, and their complete > absence on ls1043a (both of which seem to be related to copy-pasting > from other DTs). > > Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> > --- > arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 8 ++++---- > arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 8 ++++---- > arch/arm64/boot/dts/apm/apm-storm.dtsi | 8 ++++---- > arch/arm64/boot/dts/broadcom/ns2.dtsi | 8 ++++---- > arch/arm64/boot/dts/cavium/thunder-88xx.dtsi | 8 ++++---- > arch/arm64/boot/dts/exynos/exynos7.dtsi | 8 ++++---- > arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 8 ++++---- > arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 8 ++++---- > arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi | 8 ++++---- > arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 8 ++++---- > 10 files changed, 40 insertions(+), 40 deletions(-) > > diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi > index 445aa67..c2b9bcb 100644 > --- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi > +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi > @@ -255,10 +255,10 @@ > /* Local timer */ > timer { > compatible = "arm,armv8-timer"; > - interrupts = <1 13 0xf01>, > - <1 14 0xf01>, > - <1 11 0xf01>, > - <1 10 0xf01>; > + interrupts = <1 13 0xf08>, > + <1 14 0xf08>, > + <1 11 0xf08>, > + <1 10 0xf08>; For SOCFPGA: Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com> Thanks, Dinh
On 06/06/16 18:56, Marc Zyngier wrote: > The ARM architected timer specification mandates that the interrupt > associated with each timer is level triggered (which corresponds to > the "counter >= comparator" condition). > > A number of DTs are being remarkably creative, declaring the interrupt > to be edge triggered. A quick look at the TRM for the corresponding ARM > CPUs clearly shows that this is wrong, and I've corrected those. > For non-ARM designs (and in the absence of a publicly available TRM), > I've made them active low as well, which can't be completely wrong > as the GIC cannot disinguish between level low and level high. > > The respective maintainers are of course welcome to prove me wrong. > > While I was at it, I took the liberty to fix a couple of related issue, > such as some spurious affinity bits on ThunderX, and their complete > absence on ls1043a (both of which seem to be related to copy-pasting > from other DTs). > > Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> For meson-gxbb.dtsi: Acked-by: Carlo Caione <carlo@endlessm.com>
On 06/06/2016 10:56 AM, Marc Zyngier wrote: > The ARM architected timer specification mandates that the interrupt > associated with each timer is level triggered (which corresponds to > the "counter >= comparator" condition). > > A number of DTs are being remarkably creative, declaring the interrupt > to be edge triggered. A quick look at the TRM for the corresponding ARM > CPUs clearly shows that this is wrong, and I've corrected those. > For non-ARM designs (and in the absence of a publicly available TRM), > I've made them active low as well, which can't be completely wrong > as the GIC cannot disinguish between level low and level high. > > The respective maintainers are of course welcome to prove me wrong. > > While I was at it, I took the liberty to fix a couple of related issue, > such as some spurious affinity bits on ThunderX, and their complete > absence on ls1043a (both of which seem to be related to copy-pasting > from other DTs). > > Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> > --- > arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 8 ++++---- > arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 8 ++++---- > arch/arm64/boot/dts/apm/apm-storm.dtsi | 8 ++++---- > arch/arm64/boot/dts/broadcom/ns2.dtsi | 8 ++++---- > arch/arm64/boot/dts/cavium/thunder-88xx.dtsi | 8 ++++---- > arch/arm64/boot/dts/exynos/exynos7.dtsi | 8 ++++---- > arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 8 ++++---- > arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 8 ++++---- > arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi | 8 ++++---- > arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 8 ++++---- > 10 files changed, 40 insertions(+), 40 deletions(-) > [...] > diff --git a/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi b/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi > index 2eb9b22..382d86f 100644 > --- a/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi > +++ b/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi > @@ -354,10 +354,10 @@ > > timer { > compatible = "arm,armv8-timer"; > - interrupts = <1 13 0xff01>, > - <1 14 0xff01>, > - <1 11 0xff01>, > - <1 10 0xff01>; > + interrupts = <1 13 8>, > + <1 14 8>, > + <1 11 8>, > + <1 10 8>; > }; > > pmu { Acked-by: David Daney <david.daney@cavium.com>
I spoke too soon... On 06/09/2016 11:11 AM, David Daney wrote: > On 06/06/2016 10:56 AM, Marc Zyngier wrote: >> The ARM architected timer specification mandates that the interrupt >> associated with each timer is level triggered (which corresponds to >> the "counter >= comparator" condition). >> >> A number of DTs are being remarkably creative, declaring the interrupt >> to be edge triggered. A quick look at the TRM for the corresponding ARM >> CPUs clearly shows that this is wrong, and I've corrected those. >> For non-ARM designs (and in the absence of a publicly available TRM), >> I've made them active low as well, which can't be completely wrong >> as the GIC cannot disinguish between level low and level high. >> >> The respective maintainers are of course welcome to prove me wrong. >> >> While I was at it, I took the liberty to fix a couple of related issue, >> such as some spurious affinity bits on ThunderX, and their complete >> absence on ls1043a (both of which seem to be related to copy-pasting >> from other DTs). >> >> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> >> --- >> arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 8 ++++---- >> arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 8 ++++---- >> arch/arm64/boot/dts/apm/apm-storm.dtsi | 8 ++++---- >> arch/arm64/boot/dts/broadcom/ns2.dtsi | 8 ++++---- >> arch/arm64/boot/dts/cavium/thunder-88xx.dtsi | 8 ++++---- >> arch/arm64/boot/dts/exynos/exynos7.dtsi | 8 ++++---- >> arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 8 ++++---- >> arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 8 ++++---- >> arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi | 8 ++++---- >> arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 8 ++++---- >> 10 files changed, 40 insertions(+), 40 deletions(-) >> > [...] >> diff --git a/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi >> b/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi >> index 2eb9b22..382d86f 100644 >> --- a/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi >> +++ b/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi >> @@ -354,10 +354,10 @@ >> >> timer { >> compatible = "arm,armv8-timer"; >> - interrupts = <1 13 0xff01>, >> - <1 14 0xff01>, >> - <1 11 0xff01>, >> - <1 10 0xff01>; >> + interrupts = <1 13 8>, >> + <1 14 8>, >> + <1 11 8>, >> + <1 10 8>; NAK! According to arm,gic-v3.txt the trigger value must be either 1 or 4: The 3rd cell is the flags, encoded as follows: bits[3:0] trigger type and level flags. 1 = edge triggered 4 = level triggered >> }; >> >> pmu { > > Acked-by: David Daney <david.daney@cavium.com> > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
On Thu, 09 Jun 2016 14:06:02 -0700 David Daney <ddaney.cavm@gmail.com> wrote: > I spoke too soon... > > On 06/09/2016 11:11 AM, David Daney wrote: > > On 06/06/2016 10:56 AM, Marc Zyngier wrote: > >> The ARM architected timer specification mandates that the interrupt > >> associated with each timer is level triggered (which corresponds to > >> the "counter >= comparator" condition). > >> > >> A number of DTs are being remarkably creative, declaring the interrupt > >> to be edge triggered. A quick look at the TRM for the corresponding ARM > >> CPUs clearly shows that this is wrong, and I've corrected those. > >> For non-ARM designs (and in the absence of a publicly available TRM), > >> I've made them active low as well, which can't be completely wrong > >> as the GIC cannot disinguish between level low and level high. > >> > >> The respective maintainers are of course welcome to prove me wrong. > >> > >> While I was at it, I took the liberty to fix a couple of related issue, > >> such as some spurious affinity bits on ThunderX, and their complete > >> absence on ls1043a (both of which seem to be related to copy-pasting > >> from other DTs). > >> > >> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> > >> --- > >> arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 8 ++++---- > >> arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 8 ++++---- > >> arch/arm64/boot/dts/apm/apm-storm.dtsi | 8 ++++---- > >> arch/arm64/boot/dts/broadcom/ns2.dtsi | 8 ++++---- > >> arch/arm64/boot/dts/cavium/thunder-88xx.dtsi | 8 ++++---- > >> arch/arm64/boot/dts/exynos/exynos7.dtsi | 8 ++++---- > >> arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 8 ++++---- > >> arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 8 ++++---- > >> arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi | 8 ++++---- > >> arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 8 ++++---- > >> 10 files changed, 40 insertions(+), 40 deletions(-) > >> > > [...] > >> diff --git a/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi > >> b/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi > >> index 2eb9b22..382d86f 100644 > >> --- a/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi > >> +++ b/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi > >> @@ -354,10 +354,10 @@ > >> > >> timer { > >> compatible = "arm,armv8-timer"; > >> - interrupts = <1 13 0xff01>, > >> - <1 14 0xff01>, > >> - <1 11 0xff01>, > >> - <1 10 0xff01>; > >> + interrupts = <1 13 8>, > >> + <1 14 8>, > >> + <1 11 8>, > >> + <1 10 8>; > > > NAK! > > According to arm,gic-v3.txt the trigger value must be either 1 or 4: > > The 3rd cell is the flags, encoded as follows: > bits[3:0] trigger type and level flags. > 1 = edge triggered > 4 = level triggered Which is a bug in the binding description. PPIs can be any trigger (just look at the TRM for CPUs that have devices connected to a PPI to be convinced - most of them are level low). This doesn't mean that you can distinguish level-high from level-low in a programmatic way. But the HW definitely can handle it. I'll update the GICv3 binding to reflect this. Now, coming back to your NAK: is level-low the right or wrong trigger for your implementation of the architected timers? Thanks, M.
On 06/10/2016 12:23 AM, Marc Zyngier wrote: > On Thu, 09 Jun 2016 14:06:02 -0700 > David Daney <ddaney.cavm@gmail.com> wrote: > >> I spoke too soon... >> >> On 06/09/2016 11:11 AM, David Daney wrote: >>> On 06/06/2016 10:56 AM, Marc Zyngier wrote: >>>> The ARM architected timer specification mandates that the interrupt >>>> associated with each timer is level triggered (which corresponds to >>>> the "counter >= comparator" condition). >>>> >>>> A number of DTs are being remarkably creative, declaring the interrupt >>>> to be edge triggered. A quick look at the TRM for the corresponding ARM >>>> CPUs clearly shows that this is wrong, and I've corrected those. >>>> For non-ARM designs (and in the absence of a publicly available TRM), >>>> I've made them active low as well, which can't be completely wrong >>>> as the GIC cannot disinguish between level low and level high. >>>> >>>> The respective maintainers are of course welcome to prove me wrong. >>>> >>>> While I was at it, I took the liberty to fix a couple of related issue, >>>> such as some spurious affinity bits on ThunderX, and their complete >>>> absence on ls1043a (both of which seem to be related to copy-pasting >>>> from other DTs). >>>> >>>> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> >>>> --- >>>> arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 8 ++++---- >>>> arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 8 ++++---- >>>> arch/arm64/boot/dts/apm/apm-storm.dtsi | 8 ++++---- >>>> arch/arm64/boot/dts/broadcom/ns2.dtsi | 8 ++++---- >>>> arch/arm64/boot/dts/cavium/thunder-88xx.dtsi | 8 ++++---- >>>> arch/arm64/boot/dts/exynos/exynos7.dtsi | 8 ++++---- >>>> arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 8 ++++---- >>>> arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 8 ++++---- >>>> arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi | 8 ++++---- >>>> arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 8 ++++---- >>>> 10 files changed, 40 insertions(+), 40 deletions(-) >>>> >>> [...] >>>> diff --git a/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi >>>> b/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi >>>> index 2eb9b22..382d86f 100644 >>>> --- a/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi >>>> +++ b/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi >>>> @@ -354,10 +354,10 @@ >>>> >>>> timer { >>>> compatible = "arm,armv8-timer"; >>>> - interrupts = <1 13 0xff01>, >>>> - <1 14 0xff01>, >>>> - <1 11 0xff01>, >>>> - <1 10 0xff01>; >>>> + interrupts = <1 13 8>, >>>> + <1 14 8>, >>>> + <1 11 8>, >>>> + <1 10 8>; >> >> >> NAK! >> >> According to arm,gic-v3.txt the trigger value must be either 1 or 4: >> >> The 3rd cell is the flags, encoded as follows: >> bits[3:0] trigger type and level flags. >> 1 = edge triggered >> 4 = level triggered > > Which is a bug in the binding description. PPIs can be any trigger > (just look at the TRM for CPUs that have devices connected to a PPI to > be convinced - most of them are level low). > > This doesn't mean that you can distinguish level-high from level-low > in a programmatic way. But the HW definitely can handle it. > > I'll update the GICv3 binding to reflect this. > > Now, coming back to your NAK: is level-low the right or wrong trigger > for your implementation of the architected timers? > For the Cavium Thunder implementation of GIC-v3, there is no concept of high and low. All we have is asserted and not-asserted, we have chosen to map the concept of an asserted level-triggered source to IRQ_TYPE_LEVEL_HIGH, and the transition from not-asserted to asserted on an edge triggered source to IRQ_TYPE_EDGE_RISING. Looking and the code and specifications, I don't see in irq-gic-v3.c or PRD03-GENC-010745-35 any indication that the concepts of "high" and "low" exist either, although I certainly could have missed something. David Daney
On 10/06/16 17:50, David Daney wrote: > On 06/10/2016 12:23 AM, Marc Zyngier wrote: >> On Thu, 09 Jun 2016 14:06:02 -0700 >> David Daney <ddaney.cavm@gmail.com> wrote: >> >>> I spoke too soon... >>> >>> On 06/09/2016 11:11 AM, David Daney wrote: >>>> On 06/06/2016 10:56 AM, Marc Zyngier wrote: >>>>> The ARM architected timer specification mandates that the interrupt >>>>> associated with each timer is level triggered (which corresponds to >>>>> the "counter >= comparator" condition). >>>>> >>>>> A number of DTs are being remarkably creative, declaring the interrupt >>>>> to be edge triggered. A quick look at the TRM for the corresponding ARM >>>>> CPUs clearly shows that this is wrong, and I've corrected those. >>>>> For non-ARM designs (and in the absence of a publicly available TRM), >>>>> I've made them active low as well, which can't be completely wrong >>>>> as the GIC cannot disinguish between level low and level high. >>>>> >>>>> The respective maintainers are of course welcome to prove me wrong. >>>>> >>>>> While I was at it, I took the liberty to fix a couple of related issue, >>>>> such as some spurious affinity bits on ThunderX, and their complete >>>>> absence on ls1043a (both of which seem to be related to copy-pasting >>>>> from other DTs). >>>>> >>>>> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> >>>>> --- >>>>> arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 8 ++++---- >>>>> arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 8 ++++---- >>>>> arch/arm64/boot/dts/apm/apm-storm.dtsi | 8 ++++---- >>>>> arch/arm64/boot/dts/broadcom/ns2.dtsi | 8 ++++---- >>>>> arch/arm64/boot/dts/cavium/thunder-88xx.dtsi | 8 ++++---- >>>>> arch/arm64/boot/dts/exynos/exynos7.dtsi | 8 ++++---- >>>>> arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 8 ++++---- >>>>> arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 8 ++++---- >>>>> arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi | 8 ++++---- >>>>> arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 8 ++++---- >>>>> 10 files changed, 40 insertions(+), 40 deletions(-) >>>>> >>>> [...] >>>>> diff --git a/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi >>>>> b/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi >>>>> index 2eb9b22..382d86f 100644 >>>>> --- a/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi >>>>> +++ b/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi >>>>> @@ -354,10 +354,10 @@ >>>>> >>>>> timer { >>>>> compatible = "arm,armv8-timer"; >>>>> - interrupts = <1 13 0xff01>, >>>>> - <1 14 0xff01>, >>>>> - <1 11 0xff01>, >>>>> - <1 10 0xff01>; >>>>> + interrupts = <1 13 8>, >>>>> + <1 14 8>, >>>>> + <1 11 8>, >>>>> + <1 10 8>; >>> >>> >>> NAK! >>> >>> According to arm,gic-v3.txt the trigger value must be either 1 or 4: >>> >>> The 3rd cell is the flags, encoded as follows: >>> bits[3:0] trigger type and level flags. >>> 1 = edge triggered >>> 4 = level triggered >> >> Which is a bug in the binding description. PPIs can be any trigger >> (just look at the TRM for CPUs that have devices connected to a PPI to >> be convinced - most of them are level low). >> >> This doesn't mean that you can distinguish level-high from level-low >> in a programmatic way. But the HW definitely can handle it. >> >> I'll update the GICv3 binding to reflect this. >> >> Now, coming back to your NAK: is level-low the right or wrong trigger >> for your implementation of the architected timers? >> > > For the Cavium Thunder implementation of GIC-v3, there is no concept of > high and low. All we have is asserted and not-asserted, we have chosen > to map the concept of an asserted level-triggered source to > IRQ_TYPE_LEVEL_HIGH, and the transition from not-asserted to asserted on > an edge triggered source to IRQ_TYPE_EDGE_RISING. The GIC, no matter if it is from Cavium or not, doesn't have a notion of high or low indeed *from a programming interface point of view*. What matters here is the *device*, and how it is connected to the interrupt controller. And I'm pretty sure your timers are *physically* one or the other (unless they are simply floating? ;-) Thanks, M.
On 06/10/2016 09:56 AM, Marc Zyngier wrote: > On 10/06/16 17:50, David Daney wrote: >> On 06/10/2016 12:23 AM, Marc Zyngier wrote: >>> On Thu, 09 Jun 2016 14:06:02 -0700 >>> David Daney <ddaney.cavm@gmail.com> wrote: >>> >>>> I spoke too soon... >>>> >>>> On 06/09/2016 11:11 AM, David Daney wrote: >>>>> On 06/06/2016 10:56 AM, Marc Zyngier wrote: >>>>>> The ARM architected timer specification mandates that the interrupt >>>>>> associated with each timer is level triggered (which corresponds to >>>>>> the "counter >= comparator" condition). >>>>>> >>>>>> A number of DTs are being remarkably creative, declaring the interrupt >>>>>> to be edge triggered. A quick look at the TRM for the corresponding ARM >>>>>> CPUs clearly shows that this is wrong, and I've corrected those. >>>>>> For non-ARM designs (and in the absence of a publicly available TRM), >>>>>> I've made them active low as well, which can't be completely wrong >>>>>> as the GIC cannot disinguish between level low and level high. >>>>>> >>>>>> The respective maintainers are of course welcome to prove me wrong. >>>>>> >>>>>> While I was at it, I took the liberty to fix a couple of related issue, >>>>>> such as some spurious affinity bits on ThunderX, and their complete >>>>>> absence on ls1043a (both of which seem to be related to copy-pasting >>>>>> from other DTs). >>>>>> >>>>>> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> >>>>>> --- >>>>>> arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 8 ++++---- >>>>>> arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 8 ++++---- >>>>>> arch/arm64/boot/dts/apm/apm-storm.dtsi | 8 ++++---- >>>>>> arch/arm64/boot/dts/broadcom/ns2.dtsi | 8 ++++---- >>>>>> arch/arm64/boot/dts/cavium/thunder-88xx.dtsi | 8 ++++---- >>>>>> arch/arm64/boot/dts/exynos/exynos7.dtsi | 8 ++++---- >>>>>> arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 8 ++++---- >>>>>> arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 8 ++++---- >>>>>> arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi | 8 ++++---- >>>>>> arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 8 ++++---- >>>>>> 10 files changed, 40 insertions(+), 40 deletions(-) >>>>>> >>>>> [...] >>>>>> diff --git a/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi >>>>>> b/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi >>>>>> index 2eb9b22..382d86f 100644 >>>>>> --- a/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi >>>>>> +++ b/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi >>>>>> @@ -354,10 +354,10 @@ >>>>>> >>>>>> timer { >>>>>> compatible = "arm,armv8-timer"; >>>>>> - interrupts = <1 13 0xff01>, >>>>>> - <1 14 0xff01>, >>>>>> - <1 11 0xff01>, >>>>>> - <1 10 0xff01>; >>>>>> + interrupts = <1 13 8>, >>>>>> + <1 14 8>, >>>>>> + <1 11 8>, >>>>>> + <1 10 8>; >>>> >>>> >>>> NAK! >>>> >>>> According to arm,gic-v3.txt the trigger value must be either 1 or 4: >>>> >>>> The 3rd cell is the flags, encoded as follows: >>>> bits[3:0] trigger type and level flags. >>>> 1 = edge triggered >>>> 4 = level triggered >>> >>> Which is a bug in the binding description. PPIs can be any trigger >>> (just look at the TRM for CPUs that have devices connected to a PPI to >>> be convinced - most of them are level low). >>> >>> This doesn't mean that you can distinguish level-high from level-low >>> in a programmatic way. But the HW definitely can handle it. >>> >>> I'll update the GICv3 binding to reflect this. >>> >>> Now, coming back to your NAK: is level-low the right or wrong trigger >>> for your implementation of the architected timers? >>> >> >> For the Cavium Thunder implementation of GIC-v3, there is no concept of >> high and low. All we have is asserted and not-asserted, we have chosen >> to map the concept of an asserted level-triggered source to >> IRQ_TYPE_LEVEL_HIGH, and the transition from not-asserted to asserted on >> an edge triggered source to IRQ_TYPE_EDGE_RISING. > > The GIC, no matter if it is from Cavium or not, doesn't have a notion of > high or low indeed *from a programming interface point of view*. What > matters here is the *device*, and how it is connected to the interrupt > controller. And I'm pretty sure your timers are *physically* one or the > other (unless they are simply floating? ;-) > There is no wire. So the concept of measuring the voltage doesn't exist. Everything is message based (with either architecturally defined or implementation defined protocols). Let's turn the question around. What bits in the GIC-v3 registers and data structures do we need to program differently to account for the difference between IRQ_TYPE_LEVEL_HIGH and IRQ_TYPE_LEVEL_LOW? If the answer is that there are none, then allowing both to be specified, falsely implies that there is a difference and causes mental effort to be expended trying to decide which to use. Unless you can tell me that there is a bit in the GIC-v3 that depends on HIGH vs. LOW, I remain strongly opposed to changing the binding document. David Daney
On Mon, Jun 6, 2016 at 10:56 AM, Marc Zyngier <marc.zyngier@arm.com> wrote: > The ARM architected timer specification mandates that the interrupt > associated with each timer is level triggered (which corresponds to > the "counter >= comparator" condition). > > A number of DTs are being remarkably creative, declaring the interrupt > to be edge triggered. A quick look at the TRM for the corresponding ARM > CPUs clearly shows that this is wrong, and I've corrected those. > For non-ARM designs (and in the absence of a publicly available TRM), > I've made them active low as well, which can't be completely wrong > as the GIC cannot disinguish between level low and level high. > > The respective maintainers are of course welcome to prove me wrong. > > While I was at it, I took the liberty to fix a couple of related issue, > such as some spurious affinity bits on ThunderX, and their complete > absence on ls1043a (both of which seem to be related to copy-pasting > from other DTs). > > Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> > --- > arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 8 ++++---- > arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 8 ++++---- > arch/arm64/boot/dts/apm/apm-storm.dtsi | 8 ++++---- > arch/arm64/boot/dts/broadcom/ns2.dtsi | 8 ++++---- > arch/arm64/boot/dts/cavium/thunder-88xx.dtsi | 8 ++++---- > arch/arm64/boot/dts/exynos/exynos7.dtsi | 8 ++++---- > arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 8 ++++---- > arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 8 ++++---- > arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi | 8 ++++---- > arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 8 ++++---- > 10 files changed, 40 insertions(+), 40 deletions(-) > > diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi > index 445aa67..c2b9bcb 100644 > --- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi > +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi > @@ -255,10 +255,10 @@ > /* Local timer */ > timer { > compatible = "arm,armv8-timer"; > - interrupts = <1 13 0xf01>, > - <1 14 0xf01>, > - <1 11 0xf01>, > - <1 10 0xf01>; > + interrupts = <1 13 0xf08>, > + <1 14 0xf08>, > + <1 11 0xf08>, > + <1 10 0xf08>; > }; > > timer0: timer0@ffc03000 { > diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi > index 832815d..4d9d144 100644 > --- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi > +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi > @@ -100,13 +100,13 @@ > timer { > compatible = "arm,armv8-timer"; > interrupts = <GIC_PPI 13 > - (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>, > + (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, > <GIC_PPI 14 > - (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>, > + (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, > <GIC_PPI 11 > - (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>, > + (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, > <GIC_PPI 10 > - (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>; > + (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; > }; > > xtal: xtal-clk { > diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi b/arch/arm64/boot/dts/apm/apm-storm.dtsi > index 5147d76..1c4193f 100644 > --- a/arch/arm64/boot/dts/apm/apm-storm.dtsi > +++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi > @@ -110,10 +110,10 @@ > > timer { > compatible = "arm,armv8-timer"; > - interrupts = <1 0 0xff01>, /* Secure Phys IRQ */ > - <1 13 0xff01>, /* Non-secure Phys IRQ */ > - <1 14 0xff01>, /* Virt IRQ */ > - <1 15 0xff01>; /* Hyp IRQ */ > + interrupts = <1 0 0xff08>, /* Secure Phys IRQ */ > + <1 13 0xff08>, /* Non-secure Phys IRQ */ > + <1 14 0xff08>, /* Virt IRQ */ > + <1 15 0xff08>; /* Hyp IRQ */ > clock-frequency = <50000000>; > }; For above changes on apm-storm.dtsi for APM X-Gene 1: Acked-by: Duc Dang <dhdang@apm.com> Thanks, Duc Dang. > > diff --git a/arch/arm64/boot/dts/broadcom/ns2.dtsi b/arch/arm64/boot/dts/broadcom/ns2.dtsi > index ec68ec1..9c2d8a7 100644 > --- a/arch/arm64/boot/dts/broadcom/ns2.dtsi > +++ b/arch/arm64/boot/dts/broadcom/ns2.dtsi > @@ -88,13 +88,13 @@ > timer { > compatible = "arm,armv8-timer"; > interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xff) | > - IRQ_TYPE_EDGE_RISING)>, > + IRQ_TYPE_LEVEL_LOW)>, > <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xff) | > - IRQ_TYPE_EDGE_RISING)>, > + IRQ_TYPE_LEVEL_LOW)>, > <GIC_PPI 11 (GIC_CPU_MASK_RAW(0xff) | > - IRQ_TYPE_EDGE_RISING)>, > + IRQ_TYPE_LEVEL_LOW)>, > <GIC_PPI 10 (GIC_CPU_MASK_RAW(0xff) | > - IRQ_TYPE_EDGE_RISING)>; > + IRQ_TYPE_LEVEL_LOW)>; > }; > > pmu { > diff --git a/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi b/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi > index 2eb9b22..382d86f 100644 > --- a/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi > +++ b/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi > @@ -354,10 +354,10 @@ > > timer { > compatible = "arm,armv8-timer"; > - interrupts = <1 13 0xff01>, > - <1 14 0xff01>, > - <1 11 0xff01>, > - <1 10 0xff01>; > + interrupts = <1 13 8>, > + <1 14 8>, > + <1 11 8>, > + <1 10 8>; > }; > > pmu { > diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi > index ca663df..1628315 100644 > --- a/arch/arm64/boot/dts/exynos/exynos7.dtsi > +++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi > @@ -473,10 +473,10 @@ > > timer { > compatible = "arm,armv8-timer"; > - interrupts = <1 13 0xff01>, > - <1 14 0xff01>, > - <1 11 0xff01>, > - <1 10 0xff01>; > + interrupts = <1 13 0xff08>, > + <1 14 0xff08>, > + <1 11 0xff08>, > + <1 10 0xff08>; > }; > > pmu_system_controller: system-controller@105c0000 { > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi > index c277ba6..b92543d 100644 > --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi > +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi > @@ -111,10 +111,10 @@ > > timer { > compatible = "arm,armv8-timer"; > - interrupts = <1 13 0x1>, /* Physical Secure PPI */ > - <1 14 0x1>, /* Physical Non-Secure PPI */ > - <1 11 0x1>, /* Virtual PPI */ > - <1 10 0x1>; /* Hypervisor PPI */ > + interrupts = <1 13 0xf08>, /* Physical Secure PPI */ > + <1 14 0xf08>, /* Physical Non-Secure PPI */ > + <1 11 0xf08>, /* Virtual PPI */ > + <1 10 0xf08>; /* Hypervisor PPI */ > fsl,erratum-a008585; > }; > > diff --git a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi > index 20d256b..b1d6bb8 100644 > --- a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi > +++ b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi > @@ -122,10 +122,10 @@ > > timer { > compatible = "arm,armv8-timer"; > - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>, > - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>, > - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>, > - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; > + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; > }; > > odmi: odmi@300000 { > diff --git a/arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi > index 9532880..5a8e0f4 100644 > --- a/arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi > +++ b/arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi > @@ -127,10 +127,10 @@ > > timer { > compatible = "arm,armv8-timer"; > - interrupts = <1 13 0xf01>, > - <1 14 0xf01>, > - <1 11 0xf01>, > - <1 10 0xf01>; > + interrupts = <1 13 0xf08>, > + <1 14 0xf08>, > + <1 11 0xf08>, > + <1 10 0xf08>; > }; > > soc { > diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi > index e595f22..3e2e51f 100644 > --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi > +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi > @@ -65,10 +65,10 @@ > timer { > compatible = "arm,armv8-timer"; > interrupt-parent = <&gic>; > - interrupts = <1 13 0xf01>, > - <1 14 0xf01>, > - <1 11 0xf01>, > - <1 10 0xf01>; > + interrupts = <1 13 0xf08>, > + <1 14 0xf08>, > + <1 11 0xf08>, > + <1 10 0xf08>; > }; > > amba_apu { > -- > 2.1.4 >
On Fri, 10 Jun 2016 10:32:24 -0700 David Daney <ddaney@caviumnetworks.com> wrote: > On 06/10/2016 09:56 AM, Marc Zyngier wrote: > > On 10/06/16 17:50, David Daney wrote: > >> On 06/10/2016 12:23 AM, Marc Zyngier wrote: > >>> On Thu, 09 Jun 2016 14:06:02 -0700 > >>> David Daney <ddaney.cavm@gmail.com> wrote: > >>> > >>>> I spoke too soon... > >>>> > >>>> On 06/09/2016 11:11 AM, David Daney wrote: > >>>>> On 06/06/2016 10:56 AM, Marc Zyngier wrote: > >>>>>> The ARM architected timer specification mandates that the interrupt > >>>>>> associated with each timer is level triggered (which corresponds to > >>>>>> the "counter >= comparator" condition). > >>>>>> > >>>>>> A number of DTs are being remarkably creative, declaring the interrupt > >>>>>> to be edge triggered. A quick look at the TRM for the corresponding ARM > >>>>>> CPUs clearly shows that this is wrong, and I've corrected those. > >>>>>> For non-ARM designs (and in the absence of a publicly available TRM), > >>>>>> I've made them active low as well, which can't be completely wrong > >>>>>> as the GIC cannot disinguish between level low and level high. > >>>>>> > >>>>>> The respective maintainers are of course welcome to prove me wrong. > >>>>>> > >>>>>> While I was at it, I took the liberty to fix a couple of related issue, > >>>>>> such as some spurious affinity bits on ThunderX, and their complete > >>>>>> absence on ls1043a (both of which seem to be related to copy-pasting > >>>>>> from other DTs). > >>>>>> > >>>>>> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> > >>>>>> --- > >>>>>> arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 8 ++++---- > >>>>>> arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 8 ++++---- > >>>>>> arch/arm64/boot/dts/apm/apm-storm.dtsi | 8 ++++---- > >>>>>> arch/arm64/boot/dts/broadcom/ns2.dtsi | 8 ++++---- > >>>>>> arch/arm64/boot/dts/cavium/thunder-88xx.dtsi | 8 ++++---- > >>>>>> arch/arm64/boot/dts/exynos/exynos7.dtsi | 8 ++++---- > >>>>>> arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 8 ++++---- > >>>>>> arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 8 ++++---- > >>>>>> arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi | 8 ++++---- > >>>>>> arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 8 ++++---- > >>>>>> 10 files changed, 40 insertions(+), 40 deletions(-) > >>>>>> > >>>>> [...] > >>>>>> diff --git a/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi > >>>>>> b/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi > >>>>>> index 2eb9b22..382d86f 100644 > >>>>>> --- a/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi > >>>>>> +++ b/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi > >>>>>> @@ -354,10 +354,10 @@ > >>>>>> > >>>>>> timer { > >>>>>> compatible = "arm,armv8-timer"; > >>>>>> - interrupts = <1 13 0xff01>, > >>>>>> - <1 14 0xff01>, > >>>>>> - <1 11 0xff01>, > >>>>>> - <1 10 0xff01>; > >>>>>> + interrupts = <1 13 8>, > >>>>>> + <1 14 8>, > >>>>>> + <1 11 8>, > >>>>>> + <1 10 8>; > >>>> > >>>> > >>>> NAK! > >>>> > >>>> According to arm,gic-v3.txt the trigger value must be either 1 or 4: > >>>> > >>>> The 3rd cell is the flags, encoded as follows: > >>>> bits[3:0] trigger type and level flags. > >>>> 1 = edge triggered > >>>> 4 = level triggered > >>> > >>> Which is a bug in the binding description. PPIs can be any trigger > >>> (just look at the TRM for CPUs that have devices connected to a PPI to > >>> be convinced - most of them are level low). > >>> > >>> This doesn't mean that you can distinguish level-high from level-low > >>> in a programmatic way. But the HW definitely can handle it. > >>> > >>> I'll update the GICv3 binding to reflect this. > >>> > >>> Now, coming back to your NAK: is level-low the right or wrong trigger > >>> for your implementation of the architected timers? > >>> > >> > >> For the Cavium Thunder implementation of GIC-v3, there is no concept of > >> high and low. All we have is asserted and not-asserted, we have chosen > >> to map the concept of an asserted level-triggered source to > >> IRQ_TYPE_LEVEL_HIGH, and the transition from not-asserted to asserted on > >> an edge triggered source to IRQ_TYPE_EDGE_RISING. > > > > The GIC, no matter if it is from Cavium or not, doesn't have a notion of > > high or low indeed *from a programming interface point of view*. What > > matters here is the *device*, and how it is connected to the interrupt > > controller. And I'm pretty sure your timers are *physically* one or the > > other (unless they are simply floating? ;-) > > > > There is no wire. So the concept of measuring the voltage doesn't > exist. Everything is message based (with either architecturally defined > or implementation defined protocols). That's your implementation, which cannot be generalized. PPIs can perfectly be wired (and definitely *are* wires in ARM implementations) from the device all the way to the redistributor, where it effectively becomes message-based in an architecturally defined way. > Let's turn the question around. > > What bits in the GIC-v3 registers and data structures do we need to > program differently to account for the difference between > IRQ_TYPE_LEVEL_HIGH and IRQ_TYPE_LEVEL_LOW? > > If the answer is that there are none, then allowing both to be > specified, falsely implies that there is a difference and causes mental > effort to be expended trying to decide which to use. They do exist at the physical level, at least in a number of non-Cavium implementations. > > Unless you can tell me that there is a bit in the GIC-v3 that depends on > HIGH vs. LOW, I remain strongly opposed to changing the binding document. That's fine by me. I'll drop the ThunderX changes from this patch. Thanks, M.
diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi index 445aa67..c2b9bcb 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi @@ -255,10 +255,10 @@ /* Local timer */ timer { compatible = "arm,armv8-timer"; - interrupts = <1 13 0xf01>, - <1 14 0xf01>, - <1 11 0xf01>, - <1 10 0xf01>; + interrupts = <1 13 0xf08>, + <1 14 0xf08>, + <1 11 0xf08>, + <1 10 0xf08>; }; timer0: timer0@ffc03000 { diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi index 832815d..4d9d144 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi @@ -100,13 +100,13 @@ timer { compatible = "arm,armv8-timer"; interrupts = <GIC_PPI 13 - (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>, + (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 14 - (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>, + (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 11 - (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>, + (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 10 - (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>; + (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; }; xtal: xtal-clk { diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi b/arch/arm64/boot/dts/apm/apm-storm.dtsi index 5147d76..1c4193f 100644 --- a/arch/arm64/boot/dts/apm/apm-storm.dtsi +++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi @@ -110,10 +110,10 @@ timer { compatible = "arm,armv8-timer"; - interrupts = <1 0 0xff01>, /* Secure Phys IRQ */ - <1 13 0xff01>, /* Non-secure Phys IRQ */ - <1 14 0xff01>, /* Virt IRQ */ - <1 15 0xff01>; /* Hyp IRQ */ + interrupts = <1 0 0xff08>, /* Secure Phys IRQ */ + <1 13 0xff08>, /* Non-secure Phys IRQ */ + <1 14 0xff08>, /* Virt IRQ */ + <1 15 0xff08>; /* Hyp IRQ */ clock-frequency = <50000000>; }; diff --git a/arch/arm64/boot/dts/broadcom/ns2.dtsi b/arch/arm64/boot/dts/broadcom/ns2.dtsi index ec68ec1..9c2d8a7 100644 --- a/arch/arm64/boot/dts/broadcom/ns2.dtsi +++ b/arch/arm64/boot/dts/broadcom/ns2.dtsi @@ -88,13 +88,13 @@ timer { compatible = "arm,armv8-timer"; interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xff) | - IRQ_TYPE_EDGE_RISING)>, + IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xff) | - IRQ_TYPE_EDGE_RISING)>, + IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 11 (GIC_CPU_MASK_RAW(0xff) | - IRQ_TYPE_EDGE_RISING)>, + IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 10 (GIC_CPU_MASK_RAW(0xff) | - IRQ_TYPE_EDGE_RISING)>; + IRQ_TYPE_LEVEL_LOW)>; }; pmu { diff --git a/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi b/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi index 2eb9b22..382d86f 100644 --- a/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi +++ b/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi @@ -354,10 +354,10 @@ timer { compatible = "arm,armv8-timer"; - interrupts = <1 13 0xff01>, - <1 14 0xff01>, - <1 11 0xff01>, - <1 10 0xff01>; + interrupts = <1 13 8>, + <1 14 8>, + <1 11 8>, + <1 10 8>; }; pmu { diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi index ca663df..1628315 100644 --- a/arch/arm64/boot/dts/exynos/exynos7.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi @@ -473,10 +473,10 @@ timer { compatible = "arm,armv8-timer"; - interrupts = <1 13 0xff01>, - <1 14 0xff01>, - <1 11 0xff01>, - <1 10 0xff01>; + interrupts = <1 13 0xff08>, + <1 14 0xff08>, + <1 11 0xff08>, + <1 10 0xff08>; }; pmu_system_controller: system-controller@105c0000 { diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi index c277ba6..b92543d 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi @@ -111,10 +111,10 @@ timer { compatible = "arm,armv8-timer"; - interrupts = <1 13 0x1>, /* Physical Secure PPI */ - <1 14 0x1>, /* Physical Non-Secure PPI */ - <1 11 0x1>, /* Virtual PPI */ - <1 10 0x1>; /* Hypervisor PPI */ + interrupts = <1 13 0xf08>, /* Physical Secure PPI */ + <1 14 0xf08>, /* Physical Non-Secure PPI */ + <1 11 0xf08>, /* Virtual PPI */ + <1 10 0xf08>; /* Hypervisor PPI */ fsl,erratum-a008585; }; diff --git a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi index 20d256b..b1d6bb8 100644 --- a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi @@ -122,10 +122,10 @@ timer { compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>, - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>, - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>, - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; }; odmi: odmi@300000 { diff --git a/arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi index 9532880..5a8e0f4 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi @@ -127,10 +127,10 @@ timer { compatible = "arm,armv8-timer"; - interrupts = <1 13 0xf01>, - <1 14 0xf01>, - <1 11 0xf01>, - <1 10 0xf01>; + interrupts = <1 13 0xf08>, + <1 14 0xf08>, + <1 11 0xf08>, + <1 10 0xf08>; }; soc { diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index e595f22..3e2e51f 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -65,10 +65,10 @@ timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; - interrupts = <1 13 0xf01>, - <1 14 0xf01>, - <1 11 0xf01>, - <1 10 0xf01>; + interrupts = <1 13 0xf08>, + <1 14 0xf08>, + <1 11 0xf08>, + <1 10 0xf08>; }; amba_apu {
The ARM architected timer specification mandates that the interrupt associated with each timer is level triggered (which corresponds to the "counter >= comparator" condition). A number of DTs are being remarkably creative, declaring the interrupt to be edge triggered. A quick look at the TRM for the corresponding ARM CPUs clearly shows that this is wrong, and I've corrected those. For non-ARM designs (and in the absence of a publicly available TRM), I've made them active low as well, which can't be completely wrong as the GIC cannot disinguish between level low and level high. The respective maintainers are of course welcome to prove me wrong. While I was at it, I took the liberty to fix a couple of related issue, such as some spurious affinity bits on ThunderX, and their complete absence on ls1043a (both of which seem to be related to copy-pasting from other DTs). Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> --- arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 8 ++++---- arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 8 ++++---- arch/arm64/boot/dts/apm/apm-storm.dtsi | 8 ++++---- arch/arm64/boot/dts/broadcom/ns2.dtsi | 8 ++++---- arch/arm64/boot/dts/cavium/thunder-88xx.dtsi | 8 ++++---- arch/arm64/boot/dts/exynos/exynos7.dtsi | 8 ++++---- arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 8 ++++---- arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 8 ++++---- arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi | 8 ++++---- arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 8 ++++---- 10 files changed, 40 insertions(+), 40 deletions(-)