| Message ID | 1466165027-17917-13-git-send-email-jonathanh@nvidia.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Fri, Jun 17, 2016 at 01:03:46PM +0100, Jon Hunter wrote: > Populate the 'sor-safe' clock for DPAUX devices on Tegra210 that require > this clock for operation. Update the compatability string for the DPAUX > instance at address 0x545c0000 to be "nvidia,tegra210-dpaux" to ensure > that the 'sor-safe' clock is enabled for this device. Does the second DPAUX need this, too? I have a vague recollection that they were both slightly different. Thierry
On 17/06/16 17:47, Thierry Reding wrote: > * PGP Signed by an unknown key > > On Fri, Jun 17, 2016 at 01:03:46PM +0100, Jon Hunter wrote: >> Populate the 'sor-safe' clock for DPAUX devices on Tegra210 that require >> this clock for operation. Update the compatability string for the DPAUX >> instance at address 0x545c0000 to be "nvidia,tegra210-dpaux" to ensure >> that the 'sor-safe' clock is enabled for this device. > > Does the second DPAUX need this, too? I have a vague recollection that > they were both slightly different. I have assumed so, but I am checking with the h/w folks on this. Right now the TRM only describes the procedure for configuring the DPAUX pads for i2c6. I am also asking about sharing the DPAUX1 pads with i2c4. Cheers Jon
On Mon, Jun 20, 2016 at 10:23:38AM +0100, Jon Hunter wrote: > > On 17/06/16 17:47, Thierry Reding wrote: > > * PGP Signed by an unknown key > > > > On Fri, Jun 17, 2016 at 01:03:46PM +0100, Jon Hunter wrote: > >> Populate the 'sor-safe' clock for DPAUX devices on Tegra210 that require > >> this clock for operation. Update the compatability string for the DPAUX > >> instance at address 0x545c0000 to be "nvidia,tegra210-dpaux" to ensure > >> that the 'sor-safe' clock is enabled for this device. > > > > Does the second DPAUX need this, too? I have a vague recollection that > > they were both slightly different. > > I have assumed so, but I am checking with the h/w folks on this. Right > now the TRM only describes the procedure for configuring the DPAUX pads > for i2c6. I am also asking about sharing the DPAUX1 pads with i2c4. Yes, last time I looked it wasn't documented anywhere with which I2C controller the other DPAUX shared its pads. It'd be good to get all of that documented in the TRM. Thierry
diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 94f780b43037..78bcc87b627d 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -30,8 +30,9 @@ reg = <0x0 0x54040000 0x0 0x00040000>; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA210_CLK_DPAUX1>, - <&tegra_car TEGRA210_CLK_PLL_DP>; - clock-names = "dpaux", "parent"; + <&tegra_car TEGRA210_CLK_PLL_DP>, + <&tegra_car TEGRA210_CLK_SOR_SAFE>; + clock-names = "dpaux", "parent", "sor-safe"; resets = <&tegra_car 207>; reset-names = "dpaux"; power-domains = <&pd_sor>; @@ -175,12 +176,13 @@ }; dpaux: dpaux@545c0000 { - compatible = "nvidia,tegra124-dpaux"; + compatible = "nvidia,tegra210-dpaux"; reg = <0x0 0x545c0000 0x0 0x00040000>; interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA210_CLK_DPAUX>, - <&tegra_car TEGRA210_CLK_PLL_DP>; - clock-names = "dpaux", "parent"; + <&tegra_car TEGRA210_CLK_PLL_DP>, + <&tegra_car TEGRA210_CLK_SOR_SAFE>; + clock-names = "dpaux", "parent", "sor-safe"; resets = <&tegra_car 181>; reset-names = "dpaux"; power-domains = <&pd_sor>;
Populate the 'sor-safe' clock for DPAUX devices on Tegra210 that require this clock for operation. Update the compatability string for the DPAUX instance at address 0x545c0000 to be "nvidia,tegra210-dpaux" to ensure that the 'sor-safe' clock is enabled for this device. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-)