| Message ID | 1466596147-12166-2-git-send-email-dirk.behme@de.bosch.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Hi Dirk, On 22/06/16 12:49, Dirk Behme wrote: > Besides the 14MHz external clock, the SCIF might be clocked by an > internal 66MHz clock. If this is the case, the current clock source > selection breaks this configuration. Same for the settings done by > the firmware for data bits, stop bits and parity. > > Completely drop this and rely on the settings done by the firmware. > > Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com> Reviewed-by: Julien Grall <julien.grall@arm.com> Regards, > --- > xen/drivers/char/scif-uart.c | 40 ---------------------------------------- > 1 file changed, 40 deletions(-) > > diff --git a/xen/drivers/char/scif-uart.c b/xen/drivers/char/scif-uart.c > index bc157fe..f9ae257 100644 > --- a/xen/drivers/char/scif-uart.c > +++ b/xen/drivers/char/scif-uart.c > @@ -41,7 +41,6 @@ > #define scif_writew(uart, off, val) writew((val), (uart)->regs + (off)) > > static struct scif_uart { > - unsigned int data_bits, parity, stop_bits; > unsigned int irq; > char __iomem *regs; > struct irqaction irqaction; > @@ -87,7 +86,6 @@ static void scif_uart_interrupt(int irq, void *data, struct cpu_user_regs *regs) > static void __init scif_uart_init_preirq(struct serial_port *port) > { > struct scif_uart *uart = port->uart; > - uint16_t val; > > /* > * Wait until last bit has been transmitted. This is needed for a smooth > @@ -107,40 +105,6 @@ static void __init scif_uart_init_preirq(struct serial_port *port) > scif_readw(uart, SCIF_SCLSR); > scif_writew(uart, SCIF_SCLSR, 0); > > - /* Select Baud rate generator output as a clock source */ > - scif_writew(uart, SCIF_SCSCR, SCSCR_CKE10); > - > - /* Setup protocol format and Baud rate, select Asynchronous mode */ > - val = 0; > - ASSERT( uart->data_bits >= 7 && uart->data_bits <= 8 ); > - if ( uart->data_bits == 7 ) > - val |= SCSMR_CHR; > - else > - val &= ~SCSMR_CHR; > - > - ASSERT( uart->stop_bits >= 1 && uart->stop_bits <= 2 ); > - if ( uart->stop_bits == 2 ) > - val |= SCSMR_STOP; > - else > - val &= ~SCSMR_STOP; > - > - ASSERT( uart->parity >= PARITY_NONE && uart->parity <= PARITY_ODD ); > - switch ( uart->parity ) > - { > - case PARITY_NONE: > - val &= ~SCSMR_PE; > - break; > - > - case PARITY_EVEN: > - val |= SCSMR_PE; > - break; > - > - case PARITY_ODD: > - val |= SCSMR_PE | SCSMR_ODD; > - break; > - } > - scif_writew(uart, SCIF_SCSMR, val); > - > /* Setup trigger level for TX/RX FIFOs */ > scif_writew(uart, SCIF_SCFCR, SCFCR_RTRG11 | SCFCR_TTRG11); > > @@ -283,10 +247,6 @@ static int __init scif_uart_init(struct dt_device_node *dev, > > uart = &scif_com; > > - uart->data_bits = 8; > - uart->parity = PARITY_NONE; > - uart->stop_bits = 1; > - > res = dt_device_get_address(dev, 0, &addr, &size); > if ( res ) > { >
diff --git a/xen/drivers/char/scif-uart.c b/xen/drivers/char/scif-uart.c index bc157fe..f9ae257 100644 --- a/xen/drivers/char/scif-uart.c +++ b/xen/drivers/char/scif-uart.c @@ -41,7 +41,6 @@ #define scif_writew(uart, off, val) writew((val), (uart)->regs + (off)) static struct scif_uart { - unsigned int data_bits, parity, stop_bits; unsigned int irq; char __iomem *regs; struct irqaction irqaction; @@ -87,7 +86,6 @@ static void scif_uart_interrupt(int irq, void *data, struct cpu_user_regs *regs) static void __init scif_uart_init_preirq(struct serial_port *port) { struct scif_uart *uart = port->uart; - uint16_t val; /* * Wait until last bit has been transmitted. This is needed for a smooth @@ -107,40 +105,6 @@ static void __init scif_uart_init_preirq(struct serial_port *port) scif_readw(uart, SCIF_SCLSR); scif_writew(uart, SCIF_SCLSR, 0); - /* Select Baud rate generator output as a clock source */ - scif_writew(uart, SCIF_SCSCR, SCSCR_CKE10); - - /* Setup protocol format and Baud rate, select Asynchronous mode */ - val = 0; - ASSERT( uart->data_bits >= 7 && uart->data_bits <= 8 ); - if ( uart->data_bits == 7 ) - val |= SCSMR_CHR; - else - val &= ~SCSMR_CHR; - - ASSERT( uart->stop_bits >= 1 && uart->stop_bits <= 2 ); - if ( uart->stop_bits == 2 ) - val |= SCSMR_STOP; - else - val &= ~SCSMR_STOP; - - ASSERT( uart->parity >= PARITY_NONE && uart->parity <= PARITY_ODD ); - switch ( uart->parity ) - { - case PARITY_NONE: - val &= ~SCSMR_PE; - break; - - case PARITY_EVEN: - val |= SCSMR_PE; - break; - - case PARITY_ODD: - val |= SCSMR_PE | SCSMR_ODD; - break; - } - scif_writew(uart, SCIF_SCSMR, val); - /* Setup trigger level for TX/RX FIFOs */ scif_writew(uart, SCIF_SCFCR, SCFCR_RTRG11 | SCFCR_TTRG11); @@ -283,10 +247,6 @@ static int __init scif_uart_init(struct dt_device_node *dev, uart = &scif_com; - uart->data_bits = 8; - uart->parity = PARITY_NONE; - uart->stop_bits = 1; - res = dt_device_get_address(dev, 0, &addr, &size); if ( res ) {
Besides the 14MHz external clock, the SCIF might be clocked by an internal 66MHz clock. If this is the case, the current clock source selection breaks this configuration. Same for the settings done by the firmware for data bits, stop bits and parity. Completely drop this and rely on the settings done by the firmware. Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com> --- xen/drivers/char/scif-uart.c | 40 ---------------------------------------- 1 file changed, 40 deletions(-)