| Message ID | 20160625034511.7966-2-megous@megous.com (mailing list archive) |
|---|---|
| State | Rejected, archived |
| Delegated to: | Stephen Boyd |
| Headers | show |
Hi, On Sat, Jun 25, 2016 at 05:44:58AM +0200, megous@megous.com wrote: > From: Josef Gajdusek <atx@atx.name> > > This patch adds a driver for the THS clock which is present on the > Allwinner H3. > > Signed-off-by: Josef Gajdusek <atx@atx.name> You might not have noticed, but we are currently rewriting the whole clock support for the Allwinner SoCs, targetting the H3 as the first SoC to use it. There's already some support for the H3 THS clock, so please use that instead. Thanks! Maxime
Hi Maxime, I try to base everything on the torvalds's kernel. I did notice the patches. Is there some main git tree/branch where this work is tracked in? I'd gladly use it. Also there's a PLL1 rate application patch, that would need to be ported to the new CCU code, in the case I would use it as a base for this work. Given that the new CCU code is your work and it's fresh in your mind, do you have suggestion how to approach it? It is [PATCH v2 06/14] in this series. regards, o. On 25.6.2016 09:13, Maxime Ripard wrote: > Hi, > > On Sat, Jun 25, 2016 at 05:44:58AM +0200, megous@megous.com wrote: >> From: Josef Gajdusek <atx@atx.name> >> >> This patch adds a driver for the THS clock which is present on the >> Allwinner H3. >> >> Signed-off-by: Josef Gajdusek <atx@atx.name> > > You might not have noticed, but we are currently rewriting the whole > clock support for the Allwinner SoCs, targetting the H3 as the first > SoC to use it. > > There's already some support for the H3 THS clock, so please use that > instead. > > Thanks! > Maxime > -- To unsubscribe from this list: send the line "unsubscribe linux-clk" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Hi, On Sat, Jun 25, 2016 at 05:23:12PM +0200, Ondřej Jirman wrote: > Hi Maxime, > > I try to base everything on the torvalds's kernel. > > I did notice the patches. Is there some main git tree/branch where this > work is tracked in? I'd gladly use it. I just pushed it, branch sunxi/pen/clk-rework, on my github repo: https://github.com/mripard/linux > Also there's a PLL1 rate application patch, that would need to be ported > to the new CCU code, in the case I would use it as a base for this work. > Given that the new CCU code is your work and it's fresh in your mind, do > you have suggestion how to approach it? > > It is [PATCH v2 06/14] in this series. Yes, it's still in my queue of things to review, let's discuss this on this patch thread. Thanks! Maxime
diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt index 8f7619d..5faae05 100644 --- a/Documentation/devicetree/bindings/clock/sunxi.txt +++ b/Documentation/devicetree/bindings/clock/sunxi.txt @@ -87,6 +87,7 @@ Required properties: "allwinner,sun9i-a80-usb-phy-clk" - for usb phy gates + resets on A80 "allwinner,sun4i-a10-ve-clk" - for the Video Engine clock "allwinner,sun6i-a31-display-clk" - for the display clocks + "allwinner,sun8i-h3-ths-clk" - for THS on H3 Required properties for all clocks: - reg : shall be the control register address for the clock. diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile index 39d2044..8e245e3 100644 --- a/drivers/clk/sunxi/Makefile +++ b/drivers/clk/sunxi/Makefile @@ -9,6 +9,7 @@ obj-y += clk-a10-mod1.o obj-y += clk-a10-pll2.o obj-y += clk-a10-ve.o obj-y += clk-a20-gmac.o +obj-y += clk-h3-ths.o obj-y += clk-mod0.o obj-y += clk-simple-gates.o obj-y += clk-sun4i-display.o diff --git a/drivers/clk/sunxi/clk-h3-ths.c b/drivers/clk/sunxi/clk-h3-ths.c new file mode 100644 index 0000000..c1d6d32 --- /dev/null +++ b/drivers/clk/sunxi/clk-h3-ths.c @@ -0,0 +1,98 @@ +/* + * sun8i THS clock driver + * + * Copyright (C) 2015 Josef Gajdusek + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <linux/clk-provider.h> +#include <linux/of_address.h> +#include <linux/slab.h> +#include <linux/spinlock.h> + +#define SUN8I_H3_THS_CLK_ENABLE 31 +#define SUN8I_H3_THS_CLK_DIVIDER_SHIFT 0 +#define SUN8I_H3_THS_CLK_DIVIDER_WIDTH 2 + +static DEFINE_SPINLOCK(sun8i_h3_ths_clk_lock); + +static const struct clk_div_table sun8i_h3_ths_clk_table[] __initconst = { + { .val = 0, .div = 1 }, + { .val = 1, .div = 2 }, + { .val = 2, .div = 4 }, + { .val = 3, .div = 6 }, + { } /* sentinel */ +}; + +static void __init sun8i_h3_ths_clk_setup(struct device_node *node) +{ + struct clk *clk; + struct clk_gate *gate; + struct clk_divider *div; + const char *parent; + const char *clk_name = node->name; + void __iomem *reg; + int err; + + reg = of_io_request_and_map(node, 0, of_node_full_name(node)); + + if (IS_ERR(reg)) + return; + + gate = kzalloc(sizeof(*gate), GFP_KERNEL); + if (!gate) + goto err_unmap; + + div = kzalloc(sizeof(*gate), GFP_KERNEL); + if (!div) + goto err_gate_free; + + of_property_read_string(node, "clock-output-names", &clk_name); + parent = of_clk_get_parent_name(node, 0); + + gate->reg = reg; + gate->bit_idx = SUN8I_H3_THS_CLK_ENABLE; + gate->lock = &sun8i_h3_ths_clk_lock; + + div->reg = reg; + div->shift = SUN8I_H3_THS_CLK_DIVIDER_SHIFT; + div->width = SUN8I_H3_THS_CLK_DIVIDER_WIDTH; + div->table = sun8i_h3_ths_clk_table; + div->lock = &sun8i_h3_ths_clk_lock; + + clk = clk_register_composite(NULL, clk_name, &parent, 1, + NULL, NULL, + &div->hw, &clk_divider_ops, + &gate->hw, &clk_gate_ops, + CLK_SET_RATE_PARENT); + + if (IS_ERR(clk)) + goto err_div_free; + + err = of_clk_add_provider(node, of_clk_src_simple_get, clk); + if (err) + goto err_unregister_clk; + + return; + +err_unregister_clk: + clk_unregister(clk); +err_gate_free: + kfree(gate); +err_div_free: + kfree(div); +err_unmap: + iounmap(reg); +} + +CLK_OF_DECLARE(sun8i_h3_ths_clk, "allwinner,sun8i-h3-ths-clk", + sun8i_h3_ths_clk_setup);