diff mbox

[v2] drm/i915:gen9: implement WaMediaPoolStateCmdInWABB

Message ID 1467709290-5941-1-git-send-email-tim.gore@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

tim.gore@intel.com July 5, 2016, 9:01 a.m. UTC 
From: Tim Gore <tim.gore@intel.com>

This patch applies WaMediaPoolStateCmdInWABB which fixes
a problem with the restoration of thread counts on resuming
from RC6.

References: HSD#2137167
Signed-off-by: Tim Gore <tim.gore@intel.com>
---
 drivers/gpu/drm/i915/intel_lrc.c | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

Comments

Chris Wilson July 5, 2016, 9:08 a.m. UTC | #1 
On Tue, Jul 05, 2016 at 10:01:30AM +0100, tim.gore@intel.com wrote:
> From: Tim Gore <tim.gore@intel.com>
> 
> This patch applies WaMediaPoolStateCmdInWABB which fixes
> a problem with the restoration of thread counts on resuming
> from RC6.
> 
> References: HSD#2137167
> Signed-off-by: Tim Gore <tim.gore@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_lrc.c | 25 +++++++++++++++++++++++++
>  1 file changed, 25 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index 676b532..017b25c 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -1296,6 +1296,31 @@ static int gen9_init_indirectctx_bb(struct intel_engine_cs *engine,
>  		wa_ctx_emit(batch, index, 0);
>  		wa_ctx_emit(batch, index, 0);
>  	}
> +
> +	/* WaMediaPoolStateCmdInWABB:bxt */
> +	if (HAS_POOLED_EU(engine->i915)) {
> +		/*
> +		 * EU pool configuration is setup along with golden context
> +		 * during context initialization.

And then mention why we need it per-bb.

"...The EU pool however needs to be re-enabled following rc6."

So what happens when the device goes into rc6 in the middle of a batch?
-Chris
tim.gore@intel.com July 5, 2016, 9:32 a.m. UTC | #2 
Tim Gore 
Intel Corporation (UK) Ltd. - Co. Reg. #1134945 - Pipers Way, Swindon SN3 1RJ

> -----Original Message-----
> From: Chris Wilson [mailto:chris.ickle.wilson@gmail.com] On Behalf Of Chris
> Wilson
> Sent: Tuesday, July 05, 2016 10:08 AM
> To: Gore, Tim
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH v2] drm/i915:gen9: implement
> WaMediaPoolStateCmdInWABB
> 
> On Tue, Jul 05, 2016 at 10:01:30AM +0100, tim.gore@intel.com wrote:
> > From: Tim Gore <tim.gore@intel.com>
> >
> > This patch applies WaMediaPoolStateCmdInWABB which fixes a problem
> > with the restoration of thread counts on resuming from RC6.
> >
> > References: HSD#2137167
> > Signed-off-by: Tim Gore <tim.gore@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_lrc.c | 25 +++++++++++++++++++++++++
> >  1 file changed, 25 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_lrc.c
> > b/drivers/gpu/drm/i915/intel_lrc.c
> > index 676b532..017b25c 100644
> > --- a/drivers/gpu/drm/i915/intel_lrc.c
> > +++ b/drivers/gpu/drm/i915/intel_lrc.c
> > @@ -1296,6 +1296,31 @@ static int gen9_init_indirectctx_bb(struct
> intel_engine_cs *engine,
> >  		wa_ctx_emit(batch, index, 0);
> >  		wa_ctx_emit(batch, index, 0);
> >  	}
> > +
> > +	/* WaMediaPoolStateCmdInWABB:bxt */
> > +	if (HAS_POOLED_EU(engine->i915)) {
> > +		/*
> > +		 * EU pool configuration is setup along with golden context
> > +		 * during context initialization.
> 
> And then mention why we need it per-bb.
> 
> "...The EU pool however needs to be re-enabled following rc6."
> 
> So what happens when the device goes into rc6 in the middle of a batch?
> -Chris
> 
As I understand it from the email thread attached to the HSD, this workaround is
for exactly the case when we enter RC6 mid batch. When we resume, the pooled
eu mode is restored BUT this happens after the thread counts are restored, leading
to corruption of the thread counts. This workaround forces the pooled eu mode to
get "restored" (re-initialised really) before the thread counts.

  Tim
> --
> Chris Wilson, Intel Open Source Technology Centre
tim.gore@intel.com July 7, 2016, 9:48 a.m. UTC | #3 
Tim Gore 
Intel Corporation (UK) Ltd. - Co. Reg. #1134945 - Pipers Way, Swindon SN3 1RJ

> -----Original Message-----

> From: Patchwork [mailto:patchwork@emeril.freedesktop.org]

> Sent: Tuesday, July 05, 2016 10:37 AM

> To: Gore, Tim

> Cc: intel-gfx@lists.freedesktop.org

> Subject: ✗ Ro.CI.BAT: failure for drm/i915:gen9: implement

> WaMediaPoolStateCmdInWABB (rev2)

> 

> == Series Details ==

> 

> Series: drm/i915:gen9: implement WaMediaPoolStateCmdInWABB (rev2)

> URL   : https://patchwork.freedesktop.org/series/9467/

> State : failure

> 

> == Summary ==

> 

> Series 9467v2 drm/i915:gen9: implement WaMediaPoolStateCmdInWABB

> http://patchwork.freedesktop.org/api/1.0/series/9467/revisions/2/mbox

> 

> Test gem_exec_flush:

>         Subgroup basic-batch-kernel-default-cmd:

>                 pass       -> FAIL       (ro-byt-n2820)

See https://bugs.freedesktop.org/show_bug.cgi?id=95372

>         Subgroup basic-batch-kernel-default-uc:

>                 pass       -> DMESG-FAIL (ro-skl3-i5-6260u)

See https://bugs.freedesktop.org/show_bug.cgi?id=96806  , should be fixed now

>                 dmesg-fail -> PASS       (fi-skl-i7-6700k)

> Test gem_exec_suspend:

>         Subgroup basic-s3:

>                 incomplete -> PASS       (fi-snb-i7-2600)

> Test gem_mmap:

>         Subgroup basic:

>                 incomplete -> PASS       (fi-skl-i7-6700k)

> Test kms_cursor_legacy:

>         Subgroup basic-cursor-vs-flip:

>                 pass       -> FAIL       (ro-byt-n2820)

See https://bugs.freedesktop.org/show_bug.cgi?id=96701

>                 dmesg-warn -> PASS       (fi-skl-i5-6260u)

> Test kms_pipe_crc_basic:

>         Subgroup nonblocking-crc-pipe-b:

>                 pass       -> SKIP       (fi-skl-i5-6260u)

>         Subgroup nonblocking-crc-pipe-c-frame-sequence:

>                 skip       -> PASS       (fi-skl-i5-6260u)

>         Subgroup read-crc-pipe-b:

>                 skip       -> PASS       (fi-skl-i5-6260u)

> 

> fi-kbl-qkkr      total:234  pass:163  dwarn:29  dfail:0   fail:2   skip:40

> fi-skl-i5-6260u  total:234  pass:205  dwarn:0   dfail:0   fail:2   skip:27

> fi-skl-i7-6700k  total:234  pass:192  dwarn:0   dfail:0   fail:2   skip:40

> fi-snb-i7-2600   total:234  pass:178  dwarn:0   dfail:0   fail:2   skip:54

> ro-bdw-i5-5250u  total:229  pass:204  dwarn:1   dfail:1   fail:0   skip:23

> ro-bdw-i7-5600u  total:229  pass:190  dwarn:0   dfail:1   fail:0   skip:38

> ro-bsw-n3050     total:229  pass:177  dwarn:0   dfail:1   fail:2   skip:49

> ro-byt-n2820     total:229  pass:179  dwarn:0   dfail:1   fail:4   skip:45

> ro-hsw-i3-4010u  total:229  pass:197  dwarn:0   dfail:1   fail:0   skip:31

> ro-hsw-i7-4770r  total:229  pass:197  dwarn:0   dfail:1   fail:0   skip:31

> ro-ilk-i7-620lm  total:229  pass:157  dwarn:0   dfail:1   fail:1   skip:70

> ro-ilk1-i5-650   total:224  pass:157  dwarn:0   dfail:1   fail:1   skip:65

> ro-ivb-i7-3770   total:229  pass:188  dwarn:0   dfail:1   fail:0   skip:40

> ro-skl3-i5-6260u total:229  pass:207  dwarn:1   dfail:2   fail:0   skip:19

> ro-snb-i7-2620M  total:229  pass:179  dwarn:0   dfail:1   fail:1   skip:48

> ro-bdw-i7-5557U failed to connect after reboot

> 

> Results at /archive/results/CI_IGT_test/RO_Patchwork_1411/

> 

> 0a1ed46 drm-intel-nightly: 2016y-07m-04d-15h-39m-24s UTC integration

> manifest

> 8dc5715 drm/i915:gen9: implement WaMediaPoolStateCmdInWABB
arun.siluvery@linux.intel.com July 7, 2016, 1:22 p.m. UTC | #4 
On 05/07/2016 10:01, tim.gore@intel.com wrote:
> From: Tim Gore <tim.gore@intel.com>
>
> This patch applies WaMediaPoolStateCmdInWABB which fixes
> a problem with the restoration of thread counts on resuming
> from RC6.
>
> References: HSD#2137167
> Signed-off-by: Tim Gore <tim.gore@intel.com>
> ---

No code changes from v1 except for adding hsd ref.
Reviewed-by: Arun Siluvery <arun.siluvery@linux.intel.com>

regards
Arun


>   drivers/gpu/drm/i915/intel_lrc.c | 25 +++++++++++++++++++++++++
>   1 file changed, 25 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index 676b532..017b25c 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -1296,6 +1296,31 @@ static int gen9_init_indirectctx_bb(struct intel_engine_cs *engine,
>   		wa_ctx_emit(batch, index, 0);
>   		wa_ctx_emit(batch, index, 0);
>   	}
> +
> +	/* WaMediaPoolStateCmdInWABB:bxt */
> +	if (HAS_POOLED_EU(engine->i915)) {
> +		/*
> +		 * EU pool configuration is setup along with golden context
> +		 * during context initialization. This value depends on
> +		 * device type (2x6 or 3x6) and needs to be updated based
> +		 * on which subslice is disabled especially for 2x6
> +		 * devices, however it is safe to load default
> +		 * configuration of 3x6 device instead of masking off
> +		 * corresponding bits because HW ignores bits of a disabled
> +		 * subslice and drops down to appropriate config. Please
> +		 * see render_state_setup() in i915_gem_render_state.c for
> +		 * possible configurations, to avoid duplication they are
> +		 * not shown here again.
> +		 */
> +		u32 eu_pool_config = 0x00777000;
> +		wa_ctx_emit(batch, index, GEN9_MEDIA_POOL_STATE);
> +		wa_ctx_emit(batch, index, GEN9_MEDIA_POOL_ENABLE);
> +		wa_ctx_emit(batch, index, eu_pool_config);
> +		wa_ctx_emit(batch, index, 0);
> +		wa_ctx_emit(batch, index, 0);
> +		wa_ctx_emit(batch, index, 0);
> +	}
> +
>   	/* Pad to end of cacheline */
>   	while (index % CACHELINE_DWORDS)
>   		wa_ctx_emit(batch, index, MI_NOOP);
>
Tvrtko Ursulin July 7, 2016, 1:27 p.m. UTC | #5 
On 07/07/16 10:48, Gore, Tim wrote:
>> -----Original Message-----
>> From: Patchwork [mailto:patchwork@emeril.freedesktop.org]
>> Sent: Tuesday, July 05, 2016 10:37 AM
>> To: Gore, Tim
>> Cc: intel-gfx@lists.freedesktop.org
>> Subject: ✗ Ro.CI.BAT: failure for drm/i915:gen9: implement
>> WaMediaPoolStateCmdInWABB (rev2)
>>
>> == Series Details ==
>>
>> Series: drm/i915:gen9: implement WaMediaPoolStateCmdInWABB (rev2)
>> URL   : https://patchwork.freedesktop.org/series/9467/
>> State : failure
>>
>> == Summary ==
>>
>> Series 9467v2 drm/i915:gen9: implement WaMediaPoolStateCmdInWABB
>> http://patchwork.freedesktop.org/api/1.0/series/9467/revisions/2/mbox
>>
>> Test gem_exec_flush:
>>          Subgroup basic-batch-kernel-default-cmd:
>>                  pass       -> FAIL       (ro-byt-n2820)
> See https://bugs.freedesktop.org/show_bug.cgi?id=95372
>
>>          Subgroup basic-batch-kernel-default-uc:
>>                  pass       -> DMESG-FAIL (ro-skl3-i5-6260u)
> See https://bugs.freedesktop.org/show_bug.cgi?id=96806  , should be fixed now
>
>>                  dmesg-fail -> PASS       (fi-skl-i7-6700k)
>> Test gem_exec_suspend:
>>          Subgroup basic-s3:
>>                  incomplete -> PASS       (fi-snb-i7-2600)
>> Test gem_mmap:
>>          Subgroup basic:
>>                  incomplete -> PASS       (fi-skl-i7-6700k)
>> Test kms_cursor_legacy:
>>          Subgroup basic-cursor-vs-flip:
>>                  pass       -> FAIL       (ro-byt-n2820)
> See https://bugs.freedesktop.org/show_bug.cgi?id=96701
>
>>                  dmesg-warn -> PASS       (fi-skl-i5-6260u)
>> Test kms_pipe_crc_basic:
>>          Subgroup nonblocking-crc-pipe-b:
>>                  pass       -> SKIP       (fi-skl-i5-6260u)
>>          Subgroup nonblocking-crc-pipe-c-frame-sequence:
>>                  skip       -> PASS       (fi-skl-i5-6260u)
>>          Subgroup read-crc-pipe-b:
>>                  skip       -> PASS       (fi-skl-i5-6260u)
>>
>> fi-kbl-qkkr      total:234  pass:163  dwarn:29  dfail:0   fail:2   skip:40
>> fi-skl-i5-6260u  total:234  pass:205  dwarn:0   dfail:0   fail:2   skip:27
>> fi-skl-i7-6700k  total:234  pass:192  dwarn:0   dfail:0   fail:2   skip:40
>> fi-snb-i7-2600   total:234  pass:178  dwarn:0   dfail:0   fail:2   skip:54
>> ro-bdw-i5-5250u  total:229  pass:204  dwarn:1   dfail:1   fail:0   skip:23
>> ro-bdw-i7-5600u  total:229  pass:190  dwarn:0   dfail:1   fail:0   skip:38
>> ro-bsw-n3050     total:229  pass:177  dwarn:0   dfail:1   fail:2   skip:49
>> ro-byt-n2820     total:229  pass:179  dwarn:0   dfail:1   fail:4   skip:45
>> ro-hsw-i3-4010u  total:229  pass:197  dwarn:0   dfail:1   fail:0   skip:31
>> ro-hsw-i7-4770r  total:229  pass:197  dwarn:0   dfail:1   fail:0   skip:31
>> ro-ilk-i7-620lm  total:229  pass:157  dwarn:0   dfail:1   fail:1   skip:70
>> ro-ilk1-i5-650   total:224  pass:157  dwarn:0   dfail:1   fail:1   skip:65
>> ro-ivb-i7-3770   total:229  pass:188  dwarn:0   dfail:1   fail:0   skip:40
>> ro-skl3-i5-6260u total:229  pass:207  dwarn:1   dfail:2   fail:0   skip:19
>> ro-snb-i7-2620M  total:229  pass:179  dwarn:0   dfail:1   fail:1   skip:48
>> ro-bdw-i7-5557U failed to connect after reboot
>>
>> Results at /archive/results/CI_IGT_test/RO_Patchwork_1411/
>>
>> 0a1ed46 drm-intel-nightly: 2016y-07m-04d-15h-39m-24s UTC integration
>> manifest
>> 8dc5715 drm/i915:gen9: implement WaMediaPoolStateCmdInWABB

Merged to dinq, thanks for the patch and review.

Regards,

Tvrtko
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 676b532..017b25c 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1296,6 +1296,31 @@  static int gen9_init_indirectctx_bb(struct intel_engine_cs *engine,
 		wa_ctx_emit(batch, index, 0);
 		wa_ctx_emit(batch, index, 0);
 	}
+
+	/* WaMediaPoolStateCmdInWABB:bxt */
+	if (HAS_POOLED_EU(engine->i915)) {
+		/*
+		 * EU pool configuration is setup along with golden context
+		 * during context initialization. This value depends on
+		 * device type (2x6 or 3x6) and needs to be updated based
+		 * on which subslice is disabled especially for 2x6
+		 * devices, however it is safe to load default
+		 * configuration of 3x6 device instead of masking off
+		 * corresponding bits because HW ignores bits of a disabled
+		 * subslice and drops down to appropriate config. Please
+		 * see render_state_setup() in i915_gem_render_state.c for
+		 * possible configurations, to avoid duplication they are
+		 * not shown here again.
+		 */
+		u32 eu_pool_config = 0x00777000;
+		wa_ctx_emit(batch, index, GEN9_MEDIA_POOL_STATE);
+		wa_ctx_emit(batch, index, GEN9_MEDIA_POOL_ENABLE);
+		wa_ctx_emit(batch, index, eu_pool_config);
+		wa_ctx_emit(batch, index, 0);
+		wa_ctx_emit(batch, index, 0);
+		wa_ctx_emit(batch, index, 0);
+	}
+
 	/* Pad to end of cacheline */
 	while (index % CACHELINE_DWORDS)
 		wa_ctx_emit(batch, index, MI_NOOP);