| Message ID | 1469192408-21713-1-git-send-email-michael@walle.cc (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
> On 22 Jul 2016, at 15:00, Michael Walle <michael@walle.cc> wrote: > > 64 bit user mode doesn't work for the e5500 core because the MSR_CM bit is > not set which enables the 64 bit mode for this MMU model. Memory addresses > are truncated to 32 bit, which results in "Invalid data memory access" > error messages. Fix it by setting the MSR_CM bit for this MMU model. > > Signed-off-by: Michael Walle <michael@walle.cc> > --- > target-ppc/translate_init.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c > index 5ecafc7..1ebb143 100644 > --- a/target-ppc/translate_init.c > +++ b/target-ppc/translate_init.c > @@ -10218,6 +10218,9 @@ static void ppc_cpu_reset(CPUState *s) > if (env->mmu_model & POWERPC_MMU_64) { > msr |= (1ULL << MSR_SF); > } > + if (env->mmu_model == POWERPC_MMU_BOOKE206) { Is this check correct? Doesn’t e500mc adhere to 2.06 as well? Running qemu-system-ppc64 -M ppce500 -cpu e500mc … is perfectly valid and should just work. With your patch, it would start in invalid 64bit mode :). Alex
Am 2016-07-22 15:07, schrieb Alexander Graf: >> On 22 Jul 2016, at 15:00, Michael Walle <michael@walle.cc> wrote: >> >> 64 bit user mode doesn't work for the e5500 core because the MSR_CM >> bit is >> not set which enables the 64 bit mode for this MMU model. Memory >> addresses >> are truncated to 32 bit, which results in "Invalid data memory access" >> error messages. Fix it by setting the MSR_CM bit for this MMU model. >> >> Signed-off-by: Michael Walle <michael@walle.cc> >> --- >> target-ppc/translate_init.c | 3 +++ >> 1 file changed, 3 insertions(+) >> >> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c >> index 5ecafc7..1ebb143 100644 >> --- a/target-ppc/translate_init.c >> +++ b/target-ppc/translate_init.c >> @@ -10218,6 +10218,9 @@ static void ppc_cpu_reset(CPUState *s) >> if (env->mmu_model & POWERPC_MMU_64) { >> msr |= (1ULL << MSR_SF); >> } >> + if (env->mmu_model == POWERPC_MMU_BOOKE206) { > > Is this check correct? Doesn’t e500mc adhere to 2.06 as well? Running > > qemu-system-ppc64 -M ppce500 -cpu e500mc … > > is perfectly valid and should just work. With your patch, it would > start in invalid 64bit mode :). > > > Alex Mhh, sorry I don't really have any understanding of the PPC state after reset. Should have flagged this as RFC. Maybe I should explain my issue. I'm debugging a problem with the 64 bit linux-user variant (qemu-ppc64). There the first instructions causes an "Invalid data memory access" because the address is truncated to 32 bit. This is because the msr_is_64bit() returns false in my case. So first question here, is qemu-ppc64 supposed to set the MSR to 64bit mode? I guess so, because 32bit mode would be the qemu-ppc binary. What is the MSR state in full system emulation for a e5500 core? 64bit or 32bit? If it is 32bit, the simple solution would be to put #ifdef CONFIG_USER_ONLY around my patch, right? If the MMU is in 64bit mode after reset, I would have to check for the e5500, too. Mhh, I don't see that this information is available in ppc_cpu_reset(). -michael
On 07/22/2016 03:46 PM, Michael Walle wrote: > Am 2016-07-22 15:07, schrieb Alexander Graf: >>> On 22 Jul 2016, at 15:00, Michael Walle <michael@walle.cc> wrote: >>> >>> 64 bit user mode doesn't work for the e5500 core because the MSR_CM >>> bit is >>> not set which enables the 64 bit mode for this MMU model. Memory >>> addresses >>> are truncated to 32 bit, which results in "Invalid data memory access" >>> error messages. Fix it by setting the MSR_CM bit for this MMU model. >>> >>> Signed-off-by: Michael Walle <michael@walle.cc> >>> --- >>> target-ppc/translate_init.c | 3 +++ >>> 1 file changed, 3 insertions(+) >>> >>> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c >>> index 5ecafc7..1ebb143 100644 >>> --- a/target-ppc/translate_init.c >>> +++ b/target-ppc/translate_init.c >>> @@ -10218,6 +10218,9 @@ static void ppc_cpu_reset(CPUState *s) >>> if (env->mmu_model & POWERPC_MMU_64) { >>> msr |= (1ULL << MSR_SF); >>> } >>> + if (env->mmu_model == POWERPC_MMU_BOOKE206) { >> >> Is this check correct? Doesn’t e500mc adhere to 2.06 as well? Running >> >> qemu-system-ppc64 -M ppce500 -cpu e500mc … >> >> is perfectly valid and should just work. With your patch, it would >> start in invalid 64bit mode :). >> >> >> Alex > > Mhh, sorry I don't really have any understanding of the PPC state > after reset. Should have flagged this as RFC. > > Maybe I should explain my issue. I'm debugging a problem with the 64 > bit linux-user variant (qemu-ppc64). There the first instructions > causes an "Invalid data memory access" because the address is > truncated to 32 bit. This is because the msr_is_64bit() returns false > in my case. So first question here, is qemu-ppc64 supposed to set the > MSR to 64bit mode? I guess so, because 32bit mode would be the > qemu-ppc binary. What is the MSR state in full system emulation for a > e5500 core? 64bit or 32bit? It depends on the target. Usually the reset vector is used for system emulation. But apparently you're targeting user mode emulation, so the reset MSR really goes to linux-user/main.c. We already set MSR_SF there for 64bit binaries, I guess you'd have to check on the cpu flavor and just set either SF or CM depending on cpu flags (PPC2_BOOKE206 maybe?) in there. Alex > > If it is 32bit, the simple solution would be to put #ifdef > CONFIG_USER_ONLY around my patch, right? > If the MMU is in 64bit mode after reset, I would have to check for the > e5500, too. Mhh, I don't see that this information is available in > ppc_cpu_reset(). > > -michael >
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index 5ecafc7..1ebb143 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -10218,6 +10218,9 @@ static void ppc_cpu_reset(CPUState *s) if (env->mmu_model & POWERPC_MMU_64) { msr |= (1ULL << MSR_SF); } + if (env->mmu_model == POWERPC_MMU_BOOKE206) { + msr |= (1ULL << MSR_CM); + } #endif hreg_store_msr(env, msr, 1);
64 bit user mode doesn't work for the e5500 core because the MSR_CM bit is not set which enables the 64 bit mode for this MMU model. Memory addresses are truncated to 32 bit, which results in "Invalid data memory access" error messages. Fix it by setting the MSR_CM bit for this MMU model. Signed-off-by: Michael Walle <michael@walle.cc> --- target-ppc/translate_init.c | 3 +++ 1 file changed, 3 insertions(+)