| Message ID | 1469755326-10263-1-git-send-email-shawn.lin@rock-chips.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Fri, Jul 29, 2016 at 09:22:05AM +0800, Shawn Lin wrote: > This patch adds a binding that describes the Rockchip PCIe PHY > found on Rockchip SoCs PCIe interface. > > Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> > > --- > > Changes in v4: None > Changes in v3: > - rename the node to pcie_phy: pcie-phy suggested by Doug > > Changes in v2: > - add clk and reset description > - remove unit-address > > .../devicetree/bindings/phy/rockchip-pcie-phy.txt | 32 ++++++++++++++++++++++ > 1 file changed, 32 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt Please add acks when posting new versions. Rob
在 2016/7/30 5:34, Rob Herring 写道: > On Fri, Jul 29, 2016 at 09:22:05AM +0800, Shawn Lin wrote: >> This patch adds a binding that describes the Rockchip PCIe PHY >> found on Rockchip SoCs PCIe interface. >> >> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> >> >> --- >> >> Changes in v4: None >> Changes in v3: >> - rename the node to pcie_phy: pcie-phy suggested by Doug >> >> Changes in v2: >> - add clk and reset description >> - remove unit-address >> >> .../devicetree/bindings/phy/rockchip-pcie-phy.txt | 32 ++++++++++++++++++++++ >> 1 file changed, 32 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt > > Please add acks when posting new versions. yup, but I didn't see your ack for my previous version. Anyway, I will add it if needing to respin one, or Kishon could add it if all others look good to him when applying these? :) > > Rob > > >
diff --git a/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt b/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt new file mode 100644 index 0000000..aedca29 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt @@ -0,0 +1,32 @@ +Rockchip PCIE PHY +----------------------- + +Required properties: + - compatible: rockchip,rk3399-pcie-phy + - #phy-cells: must be 0 + - clocks: Must contain an entry in clock-names. + See ../clocks/clock-bindings.txt for details. + - clock-names: Must be "refclk" + - resets: Must contain an entry in reset-names. + See ../reset/reset.txt for details. + - reset-names: Must be "phy" + +Example: + +grf: syscon@ff770000 { + compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + + ... + + pcie_phy: pcie-phy { + compatible = "rockchip,rk3399-pcie-phy"; + #phy-cells = <0>; + clocks = <&cru SCLK_PCIEPHY_REF>; + clock-names = "refclk"; + resets = <&cru SRST_PCIEPHY>; + reset-names = "phy"; + }; +}; +
This patch adds a binding that describes the Rockchip PCIe PHY found on Rockchip SoCs PCIe interface. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> --- Changes in v4: None Changes in v3: - rename the node to pcie_phy: pcie-phy suggested by Doug Changes in v2: - add clk and reset description - remove unit-address .../devicetree/bindings/phy/rockchip-pcie-phy.txt | 32 ++++++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt