diff mbox

arm64: Add workaround for Cavium erratum 26026

Message ID 20160804205707.GJ2151@rric.localdomain (mailing list archive)
State New, archived
Headers show

Commit Message

Richter, Robert Aug. 4, 2016, 8:57 p.m. UTC 
The patch below is on top of Matthias' patch series:

 arm64: Implement IPI based TLB invalidation

The series is used to enable a workaround for Cavium ThunderX pass 1.x
systems.

-Robert



From abb99ee83473d9ecffb4fdaae9c69435ca670bc8 Mon Sep 17 00:00:00 2001
From: Robert Richter <rrichter@cavium.com>
Date: Fri, 29 Jul 2016 09:40:04 +0200
Subject: [PATCH] arm64: Add workaround for Cavium erratum 26026

STX may return a wrong status value if the store was successful.

This may happen on ThunderX T88 pass 1.x cpus if a broadcast TLBI is
executed on another cpu in parallel to an STX. As a result atomic or
non-blocking implementations can behave incorrectly. Use IPIs that
call local TLBIs on other cpus to avoid this.

Applies to ThunderX T88 pass 1.x cpus.

Signed-off-by: Robert Richter <rrichter@cavium.com>
---
 Documentation/arm64/silicon-errata.txt |  1 +
 arch/arm64/Kconfig                     | 14 ++++++++++++++
 arch/arm64/kernel/cpu_errata.c         |  8 ++++++++
 3 files changed, 23 insertions(+)

Comments

David Daney Aug. 4, 2016, 9:40 p.m. UTC | #1 
On 08/04/2016 01:57 PM, Robert Richter wrote:
> The patch below is on top of Matthias' patch series:
>
>   arm64: Implement IPI based TLB invalidation
>
> The series is used to enable a workaround for Cavium ThunderX pass 1.x
> systems.


Where are the rest of the patches in the series?  I would have expected 
something like "[PATCH 1/X] arm64:..." with X being greater than one.

>
> -Robert
>
>
>
>  From abb99ee83473d9ecffb4fdaae9c69435ca670bc8 Mon Sep 17 00:00:00 2001
> From: Robert Richter <rrichter@cavium.com>
> Date: Fri, 29 Jul 2016 09:40:04 +0200
> Subject: [PATCH] arm64: Add workaround for Cavium erratum 26026
>
> STX may return a wrong status value if the store was successful.
>
> This may happen on ThunderX T88 pass 1.x cpus if a broadcast TLBI is
> executed on another cpu in parallel to an STX. As a result atomic or
> non-blocking implementations can behave incorrectly. Use IPIs that
> call local TLBIs on other cpus to avoid this.
>
> Applies to ThunderX T88 pass 1.x cpus.
>
> Signed-off-by: Robert Richter <rrichter@cavium.com>
> ---
>   Documentation/arm64/silicon-errata.txt |  1 +
>   arch/arm64/Kconfig                     | 14 ++++++++++++++
>   arch/arm64/kernel/cpu_errata.c         |  8 ++++++++
>   3 files changed, 23 insertions(+)
>
> diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt
> index 4da60b463995..0d870d934528 100644
> --- a/Documentation/arm64/silicon-errata.txt
> +++ b/Documentation/arm64/silicon-errata.txt
> @@ -58,5 +58,6 @@ stable kernels.
>   | Cavium         | ThunderX ITS    | #22375, #24313  | CAVIUM_ERRATUM_22375    |
>   | Cavium         | ThunderX ITS    | #23144          | CAVIUM_ERRATUM_23144    |
>   | Cavium         | ThunderX GICv3  | #23154          | CAVIUM_ERRATUM_23154    |
> +| Cavium         | ThunderX Core   | #26026          | CAVIUM_ERRATUM_26026    |
>   | Cavium         | ThunderX Core   | #27456          | CAVIUM_ERRATUM_27456    |
>   | Cavium         | ThunderX SMMUv2 | #27704          | N/A		       |
> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
> index 5a0a691d4220..8cbd9043ec6f 100644
> --- a/arch/arm64/Kconfig
> +++ b/arch/arm64/Kconfig
> @@ -457,6 +457,20 @@ config CAVIUM_ERRATUM_23154
>
>   	  If unsure, say Y.
>
> +config CAVIUM_ERRATUM_26026
> +	bool "Cavium erratum 26026: STX may return wrong status value"
> +	default y
> +	help
> +	  STX may return a wrong status value if the store was
> +	  successful. This may happen on ThunderX T88 pass 1.x cpus if
> +	  a broadcast TLBI is executed on another cpu in parallel to
> +	  an STX. As a result atomic or non-blocking implementations
> +	  can behave incorrectly. Use IPIs that call local TLBIs on
> +	  other cpus to avoid this.
> +	  Applies to ThunderX T88 pass 1.x cpus.
> +
> +	  If unsure, say Y.
> +
>   config CAVIUM_ERRATUM_27456
>   	bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
>   	default y
> diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
> index af716b65110d..1e1753a6408e 100644
> --- a/arch/arm64/kernel/cpu_errata.c
> +++ b/arch/arm64/kernel/cpu_errata.c
> @@ -90,6 +90,14 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
>   		MIDR_RANGE(MIDR_THUNDERX, 0x00, 0x01),
>   	},
>   #endif
> +#ifdef CONFIG_CAVIUM_ERRATUM_26026
> +	{
> +	/* Cavium ThunderX, pass 1.x */
> +		.desc = "Cavium erratum 26026",
> +		.capability = ARM64_HAS_NO_BCAST_TLBI,
> +		MIDR_RANGE(MIDR_THUNDERX, 0x00, 0x01),
> +	},
> +#endif
>   #ifdef CONFIG_CAVIUM_ERRATUM_27456
>   	{
>   	/* Cavium ThunderX, T88 pass 1.x - 2.1 */
>
kernel test robot Aug. 5, 2016, 2:35 a.m. UTC | #2 
Hi Robert,

[auto build test ERROR on arm64/for-next/core]
[also build test ERROR on v4.7 next-20160804]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/Robert-Richter/arm64-Add-workaround-for-Cavium-erratum-26026/20160805-083523
base:   https://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux.git for-next/core
config: arm64-defconfig (attached as .config)
compiler: aarch64-linux-gnu-gcc (Debian 5.4.0-6) 5.4.0 20160609
reproduce:
        wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # save the attached .config to linux build tree
        make.cross ARCH=arm64 

All errors (new ones prefixed by >>):

>> arch/arm64/kernel/cpu_errata.c:99:17: error: 'ARM64_HAS_NO_BCAST_TLBI' undeclared here (not in a function)
      .capability = ARM64_HAS_NO_BCAST_TLBI,
                    ^

vim +/ARM64_HAS_NO_BCAST_TLBI +99 arch/arm64/kernel/cpu_errata.c

    93		},
    94	#endif
    95	#ifdef CONFIG_CAVIUM_ERRATUM_26026
    96		{
    97		/* Cavium ThunderX, pass 1.x */
    98			.desc = "Cavium erratum 26026",
  > 99			.capability = ARM64_HAS_NO_BCAST_TLBI,
   100			MIDR_RANGE(MIDR_THUNDERX, 0x00, 0x01),
   101		},
   102	#endif

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation
Richter, Robert Aug. 5, 2016, 7 a.m. UTC | #3 
On 04.08.16 14:40:48, David Daney wrote:
> On 08/04/2016 01:57 PM, Robert Richter wrote:
> >The patch below is on top of Matthias' patch series:
> >
> >  arm64: Implement IPI based TLB invalidation
> >
> >The series is used to enable a workaround for Cavium ThunderX pass 1.x
> >systems.
> 
> 
> Where are the rest of the patches in the series?  I would have expected
> something like "[PATCH 1/X] arm64:..." with X being greater than one.

You are cc'ed here too:

 https://lkml.org/lkml/2016/8/4/101

-Robert
David Daney Aug. 5, 2016, 4:37 p.m. UTC | #4 
On 08/05/2016 12:00 AM, Robert Richter wrote:
> On 04.08.16 14:40:48, David Daney wrote:
>> On 08/04/2016 01:57 PM, Robert Richter wrote:
>>> The patch below is on top of Matthias' patch series:
>>>
>>>   arm64: Implement IPI based TLB invalidation
>>>
>>> The series is used to enable a workaround for Cavium ThunderX pass 1.x
>>> systems.
>>
>>
>> Where are the rest of the patches in the series?  I would have expected
>> something like "[PATCH 1/X] arm64:..." with X being greater than one.
>
> You are cc'ed here too:
>
>   https://lkml.org/lkml/2016/8/4/101
>

OK, I got confused by the fact that this patch was retroactively added 
to the patch set and was missing the sequence numbering.

> -Robert
>
diff mbox

Patch

diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt
index 4da60b463995..0d870d934528 100644
--- a/Documentation/arm64/silicon-errata.txt
+++ b/Documentation/arm64/silicon-errata.txt
@@ -58,5 +58,6 @@  stable kernels.
 | Cavium         | ThunderX ITS    | #22375, #24313  | CAVIUM_ERRATUM_22375    |
 | Cavium         | ThunderX ITS    | #23144          | CAVIUM_ERRATUM_23144    |
 | Cavium         | ThunderX GICv3  | #23154          | CAVIUM_ERRATUM_23154    |
+| Cavium         | ThunderX Core   | #26026          | CAVIUM_ERRATUM_26026    |
 | Cavium         | ThunderX Core   | #27456          | CAVIUM_ERRATUM_27456    |
 | Cavium         | ThunderX SMMUv2 | #27704          | N/A		       |
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 5a0a691d4220..8cbd9043ec6f 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -457,6 +457,20 @@  config CAVIUM_ERRATUM_23154
 
 	  If unsure, say Y.
 
+config CAVIUM_ERRATUM_26026
+	bool "Cavium erratum 26026: STX may return wrong status value"
+	default y
+	help
+	  STX may return a wrong status value if the store was
+	  successful. This may happen on ThunderX T88 pass 1.x cpus if
+	  a broadcast TLBI is executed on another cpu in parallel to
+	  an STX. As a result atomic or non-blocking implementations
+	  can behave incorrectly. Use IPIs that call local TLBIs on
+	  other cpus to avoid this.
+	  Applies to ThunderX T88 pass 1.x cpus.
+
+	  If unsure, say Y.
+
 config CAVIUM_ERRATUM_27456
 	bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
 	default y
diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
index af716b65110d..1e1753a6408e 100644
--- a/arch/arm64/kernel/cpu_errata.c
+++ b/arch/arm64/kernel/cpu_errata.c
@@ -90,6 +90,14 @@  const struct arm64_cpu_capabilities arm64_errata[] = {
 		MIDR_RANGE(MIDR_THUNDERX, 0x00, 0x01),
 	},
 #endif
+#ifdef CONFIG_CAVIUM_ERRATUM_26026
+	{
+	/* Cavium ThunderX, pass 1.x */
+		.desc = "Cavium erratum 26026",
+		.capability = ARM64_HAS_NO_BCAST_TLBI,
+		MIDR_RANGE(MIDR_THUNDERX, 0x00, 0x01),
+	},
+#endif
 #ifdef CONFIG_CAVIUM_ERRATUM_27456
 	{
 	/* Cavium ThunderX, T88 pass 1.x - 2.1 */