| Message ID | 1470591415-3268-4-git-send-email-nikunj@linux.vnet.ibm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 08/07/2016 11:06 PM, Nikunj A Dadhania wrote: > +#define GEN_QEMU_LOAD_64(ldop, ext) \ > +static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \ > + TCGv_i64 val, \ > + TCGv addr) \ > +{ \ > + TCGv tmp = tcg_temp_new(); \ > + gen_qemu_##ldop(ctx, tmp, addr); \ > + tcg_gen_##ext##_tl_i64(val, tmp); \ > + tcg_temp_free(tmp); \ > } > > +GEN_QEMU_LOAD_64(ld8u, extu) > +GEN_QEMU_LOAD_64(ld16u, extu) > +GEN_QEMU_LOAD_64(ld32u, extu) > +GEN_QEMU_LOAD_64(ld32s, ext) This is a good opportunity to clean up a bit of the ppc translator and convert to the newer tcg_gen_qemu_ld_i64 function. This will eliminate the need for the extension that you're performing here. r~
Richard Henderson <rth@twiddle.net> writes: > On 08/07/2016 11:06 PM, Nikunj A Dadhania wrote: >> +#define GEN_QEMU_LOAD_64(ldop, ext) \ >> +static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \ >> + TCGv_i64 val, \ >> + TCGv addr) \ >> +{ \ >> + TCGv tmp = tcg_temp_new(); \ >> + gen_qemu_##ldop(ctx, tmp, addr); \ >> + tcg_gen_##ext##_tl_i64(val, tmp); \ >> + tcg_temp_free(tmp); \ >> } >> >> +GEN_QEMU_LOAD_64(ld8u, extu) >> +GEN_QEMU_LOAD_64(ld16u, extu) >> +GEN_QEMU_LOAD_64(ld32u, extu) >> +GEN_QEMU_LOAD_64(ld32s, ext) > > This is a good opportunity to clean up a bit of the ppc translator and convert > to the newer tcg_gen_qemu_ld_i64 function. This will eliminate the need for > the extension that you're performing here. I will have a look and change. Regards Nikunj
diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 6a79fc1..4bdf5ba 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -2495,28 +2495,29 @@ static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2) tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op); } -static void gen_qemu_ld32u_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr) -{ - TCGv tmp = tcg_temp_new(); - gen_qemu_ld32u(ctx, tmp, addr); - tcg_gen_extu_tl_i64(val, tmp); - tcg_temp_free(tmp); -} - static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2) { TCGMemOp op = MO_SL | ctx->default_tcg_memop_mask; tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op); } -static void gen_qemu_ld32s_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr) -{ - TCGv tmp = tcg_temp_new(); - gen_qemu_ld32s(ctx, tmp, addr); - tcg_gen_ext_tl_i64(val, tmp); - tcg_temp_free(tmp); + +#define GEN_QEMU_LOAD_64(ldop, ext) \ +static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \ + TCGv_i64 val, \ + TCGv addr) \ +{ \ + TCGv tmp = tcg_temp_new(); \ + gen_qemu_##ldop(ctx, tmp, addr); \ + tcg_gen_##ext##_tl_i64(val, tmp); \ + tcg_temp_free(tmp); \ } +GEN_QEMU_LOAD_64(ld8u, extu) +GEN_QEMU_LOAD_64(ld16u, extu) +GEN_QEMU_LOAD_64(ld32u, extu) +GEN_QEMU_LOAD_64(ld32s, ext) + static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) { TCGMemOp op = MO_Q | ctx->default_tcg_memop_mask; diff --git a/target-ppc/translate/vsx-impl.inc.c b/target-ppc/translate/vsx-impl.inc.c index 6e789cb..f438a50 100644 --- a/target-ppc/translate/vsx-impl.inc.c +++ b/target-ppc/translate/vsx-impl.inc.c @@ -36,6 +36,8 @@ static void gen_##name(DisasContext *ctx) \ VSX_LOAD_SCALAR(lxsdx, ld64) VSX_LOAD_SCALAR(lxsiwax, ld32s_i64) +VSX_LOAD_SCALAR(lxsibzx, ld8u_i64) +VSX_LOAD_SCALAR(lxsihzx, ld16u_i64) VSX_LOAD_SCALAR(lxsiwzx, ld32u_i64) VSX_LOAD_SCALAR(lxsspx, ld32fs) diff --git a/target-ppc/translate/vsx-ops.inc.c b/target-ppc/translate/vsx-ops.inc.c index 62a6251..4cd742c 100644 --- a/target-ppc/translate/vsx-ops.inc.c +++ b/target-ppc/translate/vsx-ops.inc.c @@ -1,6 +1,8 @@ GEN_HANDLER_E(lxsdx, 0x1F, 0x0C, 0x12, 0, PPC_NONE, PPC2_VSX), GEN_HANDLER_E(lxsiwax, 0x1F, 0x0C, 0x02, 0, PPC_NONE, PPC2_VSX207), GEN_HANDLER_E(lxsiwzx, 0x1F, 0x0C, 0x00, 0, PPC_NONE, PPC2_VSX207), +GEN_HANDLER_E(lxsibzx, 0x1F, 0x0D, 0x18, 0, PPC_NONE, PPC2_ISA300), +GEN_HANDLER_E(lxsihzx, 0x1F, 0x0D, 0x19, 0, PPC_NONE, PPC2_ISA300), GEN_HANDLER_E(lxsspx, 0x1F, 0x0C, 0x10, 0, PPC_NONE, PPC2_VSX207), GEN_HANDLER_E(lxvd2x, 0x1F, 0x0C, 0x1A, 0, PPC_NONE, PPC2_VSX), GEN_HANDLER_E(lxvdsx, 0x1F, 0x0C, 0x0A, 0, PPC_NONE, PPC2_VSX),
lxsibzx - Load VSX Scalar as Integer Byte & Zero Indexed lxsihzx - Load VSX Scalar as Integer Halfword & Zero Indexed Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> --- target-ppc/translate.c | 29 +++++++++++++++-------------- target-ppc/translate/vsx-impl.inc.c | 2 ++ target-ppc/translate/vsx-ops.inc.c | 2 ++ 3 files changed, 19 insertions(+), 14 deletions(-)