| Message ID | 1470855666-31696-3-git-send-email-nikunj@linux.vnet.ibm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 08/10/2016 08:00 PM, Nikunj A Dadhania wrote: > +#define GEN_QEMU_LOAD_64(ldop, op) \ > +static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \ > + TCGv_i64 val, \ > + TCGv addr) \ > +{ \ > + tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, \ > + op | ctx->default_tcg_memop_mask); \ > +} > + > +GEN_QEMU_LOAD_64(ld32u, MO_UL) > +GEN_QEMU_LOAD_64(ld32s, MO_SL) > > static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) > { You can of course include this last function in the cleanup as well. r~
Richard Henderson <rth@twiddle.net> writes: > On 08/10/2016 08:00 PM, Nikunj A Dadhania wrote: >> +#define GEN_QEMU_LOAD_64(ldop, op) \ >> +static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \ >> + TCGv_i64 val, \ >> + TCGv addr) \ >> +{ \ >> + tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, \ >> + op | ctx->default_tcg_memop_mask); \ >> +} >> + >> +GEN_QEMU_LOAD_64(ld32u, MO_UL) >> +GEN_QEMU_LOAD_64(ld32s, MO_SL) >> >> static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) >> { > > You can of course include this last function in the cleanup as well. Let me do this as separate patch, as it will need patching at lot of places. This will be function name change: gen_qemu_ld64 => gen_qemu_ld64_i64 I have one more patch converting load/store with reservation to qemu_st/ld. Regards, Nikunj
On 08/12/2016 05:52 AM, Nikunj A Dadhania wrote: > Richard Henderson <rth@twiddle.net> writes: > >> On 08/10/2016 08:00 PM, Nikunj A Dadhania wrote: >>> +#define GEN_QEMU_LOAD_64(ldop, op) \ >>> +static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \ >>> + TCGv_i64 val, \ >>> + TCGv addr) \ >>> +{ \ >>> + tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, \ >>> + op | ctx->default_tcg_memop_mask); \ >>> +} >>> + >>> +GEN_QEMU_LOAD_64(ld32u, MO_UL) >>> +GEN_QEMU_LOAD_64(ld32s, MO_SL) >>> >>> static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) >>> { >> >> You can of course include this last function in the cleanup as well. > > Let me do this as separate patch, as it will need patching at lot of > places. This will be function name change: gen_qemu_ld64 => > gen_qemu_ld64_i64 Oh, right, of course. r~
Richard Henderson <rth@twiddle.net> writes: > On 08/12/2016 05:52 AM, Nikunj A Dadhania wrote: >> Richard Henderson <rth@twiddle.net> writes: >> >>> On 08/10/2016 08:00 PM, Nikunj A Dadhania wrote: >>>> +#define GEN_QEMU_LOAD_64(ldop, op) \ >>>> +static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \ >>>> + TCGv_i64 val, \ >>>> + TCGv addr) \ >>>> +{ \ >>>> + tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, \ >>>> + op | ctx->default_tcg_memop_mask); \ >>>> +} >>>> + >>>> +GEN_QEMU_LOAD_64(ld32u, MO_UL) >>>> +GEN_QEMU_LOAD_64(ld32s, MO_SL) >>>> >>>> static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) >>>> { >>> >>> You can of course include this last function in the cleanup as well. >> >> Let me do this as separate patch, as it will need patching at lot of >> places. This will be function name change: gen_qemu_ld64 => >> gen_qemu_ld64_i64 > > Oh, right, of course. I have done all these changes, will send to the list after testing. Regards Nikunj
diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 2a87d1a..b00da0a 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -2462,50 +2462,32 @@ static inline void gen_align_no_le(DisasContext *ctx) } /*** Integer load ***/ -static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2) -{ - tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx); -} - -static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2) -{ - TCGMemOp op = MO_UW | ctx->default_tcg_memop_mask; - tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op); -} - -static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2) -{ - TCGMemOp op = MO_SW | ctx->default_tcg_memop_mask; - tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op); -} - -static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2) -{ - TCGMemOp op = MO_UL | ctx->default_tcg_memop_mask; - tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op); -} - -static void gen_qemu_ld32u_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr) -{ - TCGv tmp = tcg_temp_new(); - gen_qemu_ld32u(ctx, tmp, addr); - tcg_gen_extu_tl_i64(val, tmp); - tcg_temp_free(tmp); -} - -static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2) -{ - TCGMemOp op = MO_SL | ctx->default_tcg_memop_mask; - tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op); -} - -static void gen_qemu_ld32s_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr) -{ - TCGv tmp = tcg_temp_new(); - gen_qemu_ld32s(ctx, tmp, addr); - tcg_gen_ext_tl_i64(val, tmp); - tcg_temp_free(tmp); -} +#define GEN_QEMU_LOAD_TL(ldop, op) \ +static void glue(gen_qemu_, ldop)(DisasContext *ctx, \ + TCGv val, \ + TCGv addr) \ +{ \ + tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, \ + op | ctx->default_tcg_memop_mask); \ +} + +GEN_QEMU_LOAD_TL(ld8u, MO_UB) +GEN_QEMU_LOAD_TL(ld16u, MO_UW) +GEN_QEMU_LOAD_TL(ld16s, MO_SW) +GEN_QEMU_LOAD_TL(ld32u, MO_UL) +GEN_QEMU_LOAD_TL(ld32s, MO_SL) + +#define GEN_QEMU_LOAD_64(ldop, op) \ +static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \ + TCGv_i64 val, \ + TCGv addr) \ +{ \ + tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, \ + op | ctx->default_tcg_memop_mask); \ +} + +GEN_QEMU_LOAD_64(ld32u, MO_UL) +GEN_QEMU_LOAD_64(ld32s, MO_SL) static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) {
Implement macro to consolidate store operations using newer tcg_gen_qemu_ld functions. Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> --- target-ppc/translate.c | 70 +++++++++++++++++++------------------------------- 1 file changed, 26 insertions(+), 44 deletions(-)