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[v2,2/2] spi: dw: round up result of calculation for clock divider

Message ID 20160904020535.2bb2ab68@vm (mailing list archive)
State New, archived
Headers show

Commit Message

Matthias Seidel Sept. 4, 2016, 12:05 a.m. UTC
Avoid ending up with a higher frequency than requested

Signed-off-by: Matthias Seidel <kernel@mseidel.net>
---
Previously failing example:
requested transfer freq: 16MHz
max_freq = 200MHz
calculated clk_div = 12
actual frequency = 200/12 = 16.6666MHz
---
 drivers/spi/spi-dw.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

Comments

Mark Brown Sept. 6, 2016, 10:53 a.m. UTC | #1
On Sun, Sep 04, 2016 at 02:05:35AM +0200, Matthias Seidel wrote:

>  			/* clk_div doesn't support odd number */
> -			chip->clk_div = (dws->max_freq / transfer->speed_hz + 1) & 0xfffe;
> +			chip->clk_div = ((dws->max_freq + transfer->speed_hz) /
> +				transfer->speed_hz + 1) & 0xfffe;

Can we not use DIV_ROUND_UP here if that's what we're trying to do?  The
above probably needs a comment if not, I'm finding the intent rather
confusing looking at the code.
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Patch

diff --git a/drivers/spi/spi-dw.c b/drivers/spi/spi-dw.c
index c85e4b3..2fd517d 100644
--- a/drivers/spi/spi-dw.c
+++ b/drivers/spi/spi-dw.c
@@ -300,7 +300,8 @@  static int dw_spi_transfer_one(struct spi_master *master,
 	if (transfer->speed_hz != dws->current_freq) {
 		if (transfer->speed_hz != chip->speed_hz) {
 			/* clk_div doesn't support odd number */
-			chip->clk_div = (dws->max_freq / transfer->speed_hz + 1) & 0xfffe;
+			chip->clk_div = ((dws->max_freq + transfer->speed_hz) /
+				transfer->speed_hz + 1) & 0xfffe;
 			chip->speed_hz = transfer->speed_hz;
 		}
 		dws->current_freq = transfer->speed_hz;