| Message ID | 1473331794-27542-2-git-send-email-mars.cheng@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 08/09/16 11:49, Mars Cheng wrote: > This adds DT binding documentation for Mediatek MT6797. > > Signed-off-by: Mars Cheng <mars.cheng@mediatek.com> > --- > Documentation/devicetree/bindings/arm/mediatek.txt | 4 ++++ > .../bindings/arm/mediatek/mediatek,apmixedsys.txt | 1 + > .../bindings/arm/mediatek/mediatek,imgsys.txt | 1 + > .../bindings/arm/mediatek/mediatek,infracfg.txt | 1 + > .../bindings/arm/mediatek/mediatek,mmsys.txt | 1 + > .../bindings/arm/mediatek/mediatek,topckgen.txt | 1 + > .../bindings/arm/mediatek/mediatek,vdecsys.txt | 1 + > .../bindings/arm/mediatek/mediatek,vencsys.txt | 3 ++- > .../interrupt-controller/mediatek,sysirq.txt | 4 +++- > .../devicetree/bindings/serial/mtk-uart.txt | 1 + > 10 files changed, 16 insertions(+), 2 deletions(-) [...] > diff --git a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt > index 9d1d72c..3d97eb4 100644 > --- a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt > +++ b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt > @@ -8,6 +8,7 @@ Required properties: > "mediatek,mt8173-sysirq" > "mediatek,mt8135-sysirq" > "mediatek,mt8127-sysirq" > + "mediatek,mt6797-sysirq" > "mediatek,mt6795-sysirq" > "mediatek,mt6755-sysirq" > "mediatek,mt6592-sysirq" > @@ -21,7 +22,8 @@ Required properties: > - interrupt-parent: phandle of irq parent for sysirq. The parent must > use the same interrupt-cells format as GIC. > - reg: Physical base address of the intpol registers and length of memory > - mapped region. > + mapped region. Could be up to 2 registers here at max. Ex: 6797 needs 2 reg, > + others need 1. Two things: - Please make this a separate patch that can be reviewed independently of the rest of the changes, which are just adding new compatible identifiers. - Why can't you simply expose it as a separate controller? Looking at the way you're changing the corresponding driver, it looks like you're simply adding an extra base/size. If you simply had a base for the corresponding GIC interrupts, you could handle as many region as you want, and have a more generic driver. Thanks, M.
Hi Marc Thanks for your review. the response inlined. On Thu, 2016-09-08 at 13:37 +0100, Marc Zyngier wrote: > On 08/09/16 11:49, Mars Cheng wrote: > > This adds DT binding documentation for Mediatek MT6797. > > > > Signed-off-by: Mars Cheng <mars.cheng@mediatek.com> > > --- [...] > > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt > > index 9d1d72c..3d97eb4 100644 > > --- a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt > > +++ b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt > > @@ -8,6 +8,7 @@ Required properties: > > "mediatek,mt8173-sysirq" > > "mediatek,mt8135-sysirq" > > "mediatek,mt8127-sysirq" > > + "mediatek,mt6797-sysirq" > > "mediatek,mt6795-sysirq" > > "mediatek,mt6755-sysirq" > > "mediatek,mt6592-sysirq" > > @@ -21,7 +22,8 @@ Required properties: > > - interrupt-parent: phandle of irq parent for sysirq. The parent must > > use the same interrupt-cells format as GIC. > > - reg: Physical base address of the intpol registers and length of memory > > - mapped region. > > + mapped region. Could be up to 2 registers here at max. Ex: 6797 needs 2 reg, > > + others need 1. > > Two things: > > - Please make this a separate patch that can be reviewed independently > of the rest of the changes, which are just adding new compatible > identifiers. Will fix this in the next patch set. > > - Why can't you simply expose it as a separate controller? Looking at > the way you're changing the corresponding driver, it looks like you're > simply adding an extra base/size. If you simply had a base for the > corresponding GIC interrupts, you could handle as many region as you > want, and have a more generic driver. > May I know the meaning of "simply expose it as a separate controller"? Or you might like to suggest me any similar driver as a reference? I will examine it. Current design is based on the fact: We expect irq-mtk-sysirq needs the optional second base but the third one will not happen. If we really need more than 2 bases, we can figure out a more generic driver at the time, right? Thanks. > Thanks, > > M.
On 08/09/16 15:08, Mars Cheng wrote: > Hi Marc > > Thanks for your review. the response inlined. > > On Thu, 2016-09-08 at 13:37 +0100, Marc Zyngier wrote: >> On 08/09/16 11:49, Mars Cheng wrote: >>> This adds DT binding documentation for Mediatek MT6797. >>> >>> Signed-off-by: Mars Cheng <mars.cheng@mediatek.com> >>> --- > [...] >> >>> diff --git a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt >>> index 9d1d72c..3d97eb4 100644 >>> --- a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt >>> +++ b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt >>> @@ -8,6 +8,7 @@ Required properties: >>> "mediatek,mt8173-sysirq" >>> "mediatek,mt8135-sysirq" >>> "mediatek,mt8127-sysirq" >>> + "mediatek,mt6797-sysirq" >>> "mediatek,mt6795-sysirq" >>> "mediatek,mt6755-sysirq" >>> "mediatek,mt6592-sysirq" >>> @@ -21,7 +22,8 @@ Required properties: >>> - interrupt-parent: phandle of irq parent for sysirq. The parent must >>> use the same interrupt-cells format as GIC. >>> - reg: Physical base address of the intpol registers and length of memory >>> - mapped region. >>> + mapped region. Could be up to 2 registers here at max. Ex: 6797 needs 2 reg, >>> + others need 1. >> >> Two things: >> >> - Please make this a separate patch that can be reviewed independently >> of the rest of the changes, which are just adding new compatible >> identifiers. > > Will fix this in the next patch set. > >> >> - Why can't you simply expose it as a separate controller? Looking at >> the way you're changing the corresponding driver, it looks like you're >> simply adding an extra base/size. If you simply had a base for the >> corresponding GIC interrupts, you could handle as many region as you >> want, and have a more generic driver. >> > > May I know the meaning of "simply expose it as a separate controller"? At the moment, you have something like this: sysirq: intpol-controller@10200620 { compatible = "mediatek,mt6755-sysirq", "mediatek,mt6577-sysirq"; interrupt-controller; #interrupt-cells = <3>; interrupt-parent = <&gic>; reg = <0 0x10200620 0 0x20>; }; I suggest that, when you have a second base (which is effectively another controller), you add: sysirq2: intpol-controller@10201620 { compatible = "mediatek,mt6755-sysirq", "mediatek,mt6577-sysirq"; interrupt-controller; #interrupt-cells = <3>; interrupt-parent = <&gic>; irq-base = <32>; reg = <0 0x10201620 0 0x20>; }; Where irq-base is the first SPI this is connected to (the lack of property indicates implies that irq-base is 0). This becomes a very simple change in the driver. > Or you might like to suggest me any similar driver as a reference? I > will examine it. Current design is based on the fact: We expect > irq-mtk-sysirq needs the optional second base but the third one will not > happen. > > If we really need more than 2 bases, we can figure out a more generic > driver at the time, right? I'd rather fix the driver and the binding to do the right thing once and for all. In my experience, you will need to add a third base in six months, and a fourth soon after. I'd rather either support an arbitrary number of bases, or a single one per controller (and have multiple controllers). Thanks, M.
On Thu, 2016-09-08 at 15:32 +0100, Marc Zyngier wrote: > On 08/09/16 15:08, Mars Cheng wrote: > > Hi Marc > > > > Thanks for your review. the response inlined. > > > > On Thu, 2016-09-08 at 13:37 +0100, Marc Zyngier wrote: > >> On 08/09/16 11:49, Mars Cheng wrote: > >>> This adds DT binding documentation for Mediatek MT6797. > >>> > >>> Signed-off-by: Mars Cheng <mars.cheng@mediatek.com> > >>> --- > > [...] > >> > >>> diff --git a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt > >>> index 9d1d72c..3d97eb4 100644 > >>> --- a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt > >>> +++ b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt > >>> @@ -8,6 +8,7 @@ Required properties: > >>> "mediatek,mt8173-sysirq" > >>> "mediatek,mt8135-sysirq" > >>> "mediatek,mt8127-sysirq" > >>> + "mediatek,mt6797-sysirq" > >>> "mediatek,mt6795-sysirq" > >>> "mediatek,mt6755-sysirq" > >>> "mediatek,mt6592-sysirq" > >>> @@ -21,7 +22,8 @@ Required properties: > >>> - interrupt-parent: phandle of irq parent for sysirq. The parent must > >>> use the same interrupt-cells format as GIC. > >>> - reg: Physical base address of the intpol registers and length of memory > >>> - mapped region. > >>> + mapped region. Could be up to 2 registers here at max. Ex: 6797 needs 2 reg, > >>> + others need 1. > >> > >> Two things: > >> > >> - Please make this a separate patch that can be reviewed independently > >> of the rest of the changes, which are just adding new compatible > >> identifiers. > > > > Will fix this in the next patch set. > > > >> > >> - Why can't you simply expose it as a separate controller? Looking at > >> the way you're changing the corresponding driver, it looks like you're > >> simply adding an extra base/size. If you simply had a base for the > >> corresponding GIC interrupts, you could handle as many region as you > >> want, and have a more generic driver. > >> > > > > May I know the meaning of "simply expose it as a separate controller"? > > At the moment, you have something like this: > > sysirq: intpol-controller@10200620 { > compatible = "mediatek,mt6755-sysirq", > "mediatek,mt6577-sysirq"; > interrupt-controller; > #interrupt-cells = <3>; > interrupt-parent = <&gic>; > reg = <0 0x10200620 0 0x20>; > }; > > I suggest that, when you have a second base (which is effectively > another controller), you add: > > sysirq2: intpol-controller@10201620 { > compatible = "mediatek,mt6755-sysirq", > "mediatek,mt6577-sysirq"; > interrupt-controller; > #interrupt-cells = <3>; > interrupt-parent = <&gic>; > irq-base = <32>; > reg = <0 0x10201620 0 0x20>; > }; > > Where irq-base is the first SPI this is connected to (the lack of > property indicates implies that irq-base is 0). This becomes a very > simple change in the driver. > > > Or you might like to suggest me any similar driver as a reference? I > > will examine it. Current design is based on the fact: We expect > > irq-mtk-sysirq needs the optional second base but the third one will not > > happen. > > > > If we really need more than 2 bases, we can figure out a more generic > > driver at the time, right? > > I'd rather fix the driver and the binding to do the right thing once and > for all. In my experience, you will need to add a third base in six > months, and a fourth soon after. I'd rather either support an arbitrary > number of bases, or a single one per controller (and have multiple > controllers). Hi Marc Thanks for suggesting this approach I never thought. However, I will modify the irq-mtk-sysirq driver to handle as many bases as we specify in current node in the next patch set. Will not use the second interrupt node in DT. The main reason is to simplify the writing of DT. Or we need to know which interrupt node to be specified for other nodes. As you said that might be the third or fourth bases, that will complicate the writing of DT more. Would you think this is OK? Thanks. > > Thanks, > > M.
On 12/09/16 02:51, Mars Cheng wrote: > On Thu, 2016-09-08 at 15:32 +0100, Marc Zyngier wrote: >> On 08/09/16 15:08, Mars Cheng wrote: >>> Hi Marc >>> >>> Thanks for your review. the response inlined. >>> >>> On Thu, 2016-09-08 at 13:37 +0100, Marc Zyngier wrote: >>>> On 08/09/16 11:49, Mars Cheng wrote: >>>>> This adds DT binding documentation for Mediatek MT6797. >>>>> >>>>> Signed-off-by: Mars Cheng <mars.cheng@mediatek.com> >>>>> --- >>> [...] >>>> >>>>> diff --git a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt >>>>> index 9d1d72c..3d97eb4 100644 >>>>> --- a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt >>>>> +++ b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt >>>>> @@ -8,6 +8,7 @@ Required properties: >>>>> "mediatek,mt8173-sysirq" >>>>> "mediatek,mt8135-sysirq" >>>>> "mediatek,mt8127-sysirq" >>>>> + "mediatek,mt6797-sysirq" >>>>> "mediatek,mt6795-sysirq" >>>>> "mediatek,mt6755-sysirq" >>>>> "mediatek,mt6592-sysirq" >>>>> @@ -21,7 +22,8 @@ Required properties: >>>>> - interrupt-parent: phandle of irq parent for sysirq. The parent must >>>>> use the same interrupt-cells format as GIC. >>>>> - reg: Physical base address of the intpol registers and length of memory >>>>> - mapped region. >>>>> + mapped region. Could be up to 2 registers here at max. Ex: 6797 needs 2 reg, >>>>> + others need 1. >>>> >>>> Two things: >>>> >>>> - Please make this a separate patch that can be reviewed independently >>>> of the rest of the changes, which are just adding new compatible >>>> identifiers. >>> >>> Will fix this in the next patch set. >>> >>>> >>>> - Why can't you simply expose it as a separate controller? Looking at >>>> the way you're changing the corresponding driver, it looks like you're >>>> simply adding an extra base/size. If you simply had a base for the >>>> corresponding GIC interrupts, you could handle as many region as you >>>> want, and have a more generic driver. >>>> >>> >>> May I know the meaning of "simply expose it as a separate controller"? >> >> At the moment, you have something like this: >> >> sysirq: intpol-controller@10200620 { >> compatible = "mediatek,mt6755-sysirq", >> "mediatek,mt6577-sysirq"; >> interrupt-controller; >> #interrupt-cells = <3>; >> interrupt-parent = <&gic>; >> reg = <0 0x10200620 0 0x20>; >> }; >> >> I suggest that, when you have a second base (which is effectively >> another controller), you add: >> >> sysirq2: intpol-controller@10201620 { >> compatible = "mediatek,mt6755-sysirq", >> "mediatek,mt6577-sysirq"; >> interrupt-controller; >> #interrupt-cells = <3>; >> interrupt-parent = <&gic>; >> irq-base = <32>; >> reg = <0 0x10201620 0 0x20>; >> }; >> >> Where irq-base is the first SPI this is connected to (the lack of >> property indicates implies that irq-base is 0). This becomes a very >> simple change in the driver. >> >>> Or you might like to suggest me any similar driver as a reference? I >>> will examine it. Current design is based on the fact: We expect >>> irq-mtk-sysirq needs the optional second base but the third one will not >>> happen. >>> >>> If we really need more than 2 bases, we can figure out a more generic >>> driver at the time, right? >> >> I'd rather fix the driver and the binding to do the right thing once and >> for all. In my experience, you will need to add a third base in six >> months, and a fourth soon after. I'd rather either support an arbitrary >> number of bases, or a single one per controller (and have multiple >> controllers). > Hi Marc > > Thanks for suggesting this approach I never thought. > > However, I will modify the irq-mtk-sysirq driver to handle as many bases > as we specify in current node in the next patch set. Will not use the > second interrupt node in DT. The main reason is to simplify the writing > of DT. Or we need to know which interrupt node to be specified for other > nodes. As you said that might be the third or fourth bases, that will > complicate the writing of DT more. > > Would you think this is OK? There is still one thing that is not completely obvious to me: How do you map a new set of registers to the corresponding base GIC SPI? At the moment, this is an implicit SPI0 (hwirq 32 on the GIC). I don't think assuming that all the banks will forever be contiguous is a safe bet, so introducing some form of sparseness support seems beneficial. As for simplifying the DT, I'm not convinced either. You already deal with two interrupt controllers (the GIC and this intpol), which means you need to locally annotate some DT nodes to point to the GIC. With my scheme, you keep annotating more (or use the extended interrupt specifier notation), but that doesn't feel like a massive burden. How often do you write a DT from scratch? Anyway, this is up to you. My only requirements is about being able to support an arbitrary numbers of register sets, with arbitrary SPI bases. Thanks, M.
diff --git a/Documentation/devicetree/bindings/arm/mediatek.txt b/Documentation/devicetree/bindings/arm/mediatek.txt index c860b24..2d3344d 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.txt +++ b/Documentation/devicetree/bindings/arm/mediatek.txt @@ -12,6 +12,7 @@ compatible: Must contain one of "mediatek,mt6592" "mediatek,mt6755" "mediatek,mt6795" + "mediatek,mt6797" "mediatek,mt7623" "mediatek,mt8127" "mediatek,mt8135" @@ -38,6 +39,9 @@ Supported boards: - Evaluation board for MT6795(Helio X10): Required root node properties: - compatible = "mediatek,mt6795-evb", "mediatek,mt6795"; +- Evaluation board for MT6797(Helio X20): + Required root node properties: + - compatible = "mediatek,mt6797-evb", "mediatek,mt6797"; - Evaluation board for MT7623: Required root node properties: - compatible = "mediatek,mt7623-evb", "mediatek,mt7623"; diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt index cb0054a..cd977db 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt @@ -7,6 +7,7 @@ Required Properties: - compatible: Should be one of: - "mediatek,mt2701-apmixedsys" + - "mediatek,mt6797-apmixedsys" - "mediatek,mt8135-apmixedsys" - "mediatek,mt8173-apmixedsys" - #clock-cells: Must be 1 diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt index f6a9166..047b11a 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt @@ -7,6 +7,7 @@ Required Properties: - compatible: Should be one of: - "mediatek,mt2701-imgsys", "syscon" + - "mediatek,mt6797-imgsys", "syscon" - "mediatek,mt8173-imgsys", "syscon" - #clock-cells: Must be 1 diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt index 1620ec2..58d58e2 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt @@ -8,6 +8,7 @@ Required Properties: - compatible: Should be one of: - "mediatek,mt2701-infracfg", "syscon" + - "mediatek,mt6797-infracfg", "syscon" - "mediatek,mt8135-infracfg", "syscon" - "mediatek,mt8173-infracfg", "syscon" - #clock-cells: Must be 1 diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt index 67dd2e4..70529e0 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt @@ -7,6 +7,7 @@ Required Properties: - compatible: Should be one of: - "mediatek,mt2701-mmsys", "syscon" + - "mediatek,mt6797-mmsys", "syscon" - "mediatek,mt8173-mmsys", "syscon" - #clock-cells: Must be 1 diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt index 9f2fe78..ec93ecb 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt @@ -7,6 +7,7 @@ Required Properties: - compatible: Should be one of: - "mediatek,mt2701-topckgen" + - "mediatek,mt6797-topckgen" - "mediatek,mt8135-topckgen" - "mediatek,mt8173-topckgen" - #clock-cells: Must be 1 diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys.txt index 2440f73..d150104 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys.txt @@ -7,6 +7,7 @@ Required Properties: - compatible: Should be one of: - "mediatek,mt2701-vdecsys", "syscon" + - "mediatek,mt6797-vdecsys", "syscon" - "mediatek,mt8173-vdecsys", "syscon" - #clock-cells: Must be 1 diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,vencsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,vencsys.txt index 5bb2866..8a93be6 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,vencsys.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,vencsys.txt @@ -5,7 +5,8 @@ The Mediatek vencsys controller provides various clocks to the system. Required Properties: -- compatible: Should be: +- compatible: Should be one of: + - "mediatek,mt6797-vencsys", "syscon" - "mediatek,mt8173-vencsys", "syscon" - #clock-cells: Must be 1 diff --git a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt index 9d1d72c..3d97eb4 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt @@ -8,6 +8,7 @@ Required properties: "mediatek,mt8173-sysirq" "mediatek,mt8135-sysirq" "mediatek,mt8127-sysirq" + "mediatek,mt6797-sysirq" "mediatek,mt6795-sysirq" "mediatek,mt6755-sysirq" "mediatek,mt6592-sysirq" @@ -21,7 +22,8 @@ Required properties: - interrupt-parent: phandle of irq parent for sysirq. The parent must use the same interrupt-cells format as GIC. - reg: Physical base address of the intpol registers and length of memory - mapped region. + mapped region. Could be up to 2 registers here at max. Ex: 6797 needs 2 reg, + others need 1. Example: sysirq: interrupt-controller@10200100 { diff --git a/Documentation/devicetree/bindings/serial/mtk-uart.txt b/Documentation/devicetree/bindings/serial/mtk-uart.txt index 0015c72..a1dbb62 100644 --- a/Documentation/devicetree/bindings/serial/mtk-uart.txt +++ b/Documentation/devicetree/bindings/serial/mtk-uart.txt @@ -8,6 +8,7 @@ Required properties: * "mediatek,mt6589-uart" for MT6589 compatible UARTS * "mediatek,mt6755-uart" for MT6755 compatible UARTS * "mediatek,mt6795-uart" for MT6795 compatible UARTS + * "mediatek,mt6797-uart" for MT6795 compatible UARTS * "mediatek,mt7623-uart" for MT7623 compatible UARTS * "mediatek,mt8127-uart" for MT8127 compatible UARTS * "mediatek,mt8135-uart" for MT8135 compatible UARTS
This adds DT binding documentation for Mediatek MT6797. Signed-off-by: Mars Cheng <mars.cheng@mediatek.com> --- Documentation/devicetree/bindings/arm/mediatek.txt | 4 ++++ .../bindings/arm/mediatek/mediatek,apmixedsys.txt | 1 + .../bindings/arm/mediatek/mediatek,imgsys.txt | 1 + .../bindings/arm/mediatek/mediatek,infracfg.txt | 1 + .../bindings/arm/mediatek/mediatek,mmsys.txt | 1 + .../bindings/arm/mediatek/mediatek,topckgen.txt | 1 + .../bindings/arm/mediatek/mediatek,vdecsys.txt | 1 + .../bindings/arm/mediatek/mediatek,vencsys.txt | 3 ++- .../interrupt-controller/mediatek,sysirq.txt | 4 +++- .../devicetree/bindings/serial/mtk-uart.txt | 1 + 10 files changed, 16 insertions(+), 2 deletions(-)