| Message ID | 1473447580-10369-4-git-send-email-ayaka@soulik.info (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Hello. On 09/09/2016 09:59 PM, Randy Li wrote: > On the rk3288 USB host-only port (the one that's not the OTG-enabled > port) the PHY can get into a bad state when a wakeup is asserted (not > just a wakeup from full system suspend but also a wakeup from > autosuspend). > > We can get the PHY out of its bad state by asserting its "port reset", > but unfortunately that seems to assert a reset onto the USB bus so it > could confuse things if we don't actually deenumerate / reenumerate the > device. > > We can also get the PHY out of its bad state by fully resetting it using > the reset from the CRU (clock reset unit) in chip, which does a more full > reset. The CRU-based reset appears to actually cause devices on the bus > to be removed and reinserted, which fixes the problem (albeit in a hacky > way). > > It's unfortunate that we need to do a full re-enumeration of devices at > wakeup time, but this is better than alternative of letting the bus get > wedged. > > Signed-off-by: Randy Li <ayaka@soulik.info> > --- > drivers/usb/dwc2/core_intr.c | 11 +++++++++++ > 1 file changed, 11 insertions(+) > > diff --git a/drivers/usb/dwc2/core_intr.c b/drivers/usb/dwc2/core_intr.c > index d85c5c9..af27edc 100644 > --- a/drivers/usb/dwc2/core_intr.c > +++ b/drivers/usb/dwc2/core_intr.c [...] > @@ -379,6 +380,16 @@ static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg) > /* Restart the Phy Clock */ > pcgcctl &= ~PCGCTL_STOPPCLK; > dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); > + > + /* > + * It is a quirk in Rockchip RK3288, causing by Caused. [...] MBR, Sergei
Hi Randy,
[auto build test ERROR on rockchip/for-next]
[also build test ERROR on v4.8-rc5 next-20160909]
[cannot apply to phy/next]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
[Suggest to use git(>=2.9.0) format-patch --base=<commit> (or --base=auto for convenience) to record what (public, well-known) commit your patch series was built on]
[Check https://git-scm.com/docs/git-format-patch for more information]
url: https://github.com/0day-ci/linux/commits/Randy-Li/the-fix-for-the-USB-HOST1-at-rk3288-platform/20160910-030348
base: https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git for-next
config: arm-socfpga_defconfig (attached as .config)
compiler: arm-linux-gnueabi-gcc (Debian 5.4.0-6) 5.4.0 20160609
reproduce:
wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=arm
All errors (new ones prefixed by >>):
drivers/usb/dwc2/core_intr.c: In function 'dwc2_handle_wakeup_detected_intr':
>> drivers/usb/dwc2/core_intr.c:391:5: error: implicit declaration of function 'phy_reset' [-Werror=implicit-function-declaration]
phy_reset(hsotg->phy);
^
cc1: some warnings being treated as errors
vim +/phy_reset +391 drivers/usb/dwc2/core_intr.c
385 * It is a quirk in Rockchip RK3288, causing by
386 * a hardware bug. This will propagate out and
387 * eventually we'll re-enumerate the device.
388 * Not great but the best we can do.
389 */
390 if (of_device_is_compatible(np, "rockchip,rk3288-usb"))
> 391 phy_reset(hsotg->phy);
392
393 mod_timer(&hsotg->wkp_timer,
394 jiffies + msecs_to_jiffies(71));
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
diff --git a/drivers/usb/dwc2/core_intr.c b/drivers/usb/dwc2/core_intr.c index d85c5c9..af27edc 100644 --- a/drivers/usb/dwc2/core_intr.c +++ b/drivers/usb/dwc2/core_intr.c @@ -345,6 +345,7 @@ static void dwc2_handle_session_req_intr(struct dwc2_hsotg *hsotg) static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg) { int ret; + struct device_node *np = hsotg->dev->of_node; /* Clear interrupt */ dwc2_writel(GINTSTS_WKUPINT, hsotg->regs + GINTSTS); @@ -379,6 +380,16 @@ static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg) /* Restart the Phy Clock */ pcgcctl &= ~PCGCTL_STOPPCLK; dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); + + /* + * It is a quirk in Rockchip RK3288, causing by + * a hardware bug. This will propagate out and + * eventually we'll re-enumerate the device. + * Not great but the best we can do. + */ + if (of_device_is_compatible(np, "rockchip,rk3288-usb")) + phy_reset(hsotg->phy); + mod_timer(&hsotg->wkp_timer, jiffies + msecs_to_jiffies(71)); } else {
On the rk3288 USB host-only port (the one that's not the OTG-enabled port) the PHY can get into a bad state when a wakeup is asserted (not just a wakeup from full system suspend but also a wakeup from autosuspend). We can get the PHY out of its bad state by asserting its "port reset", but unfortunately that seems to assert a reset onto the USB bus so it could confuse things if we don't actually deenumerate / reenumerate the device. We can also get the PHY out of its bad state by fully resetting it using the reset from the CRU (clock reset unit) in chip, which does a more full reset. The CRU-based reset appears to actually cause devices on the bus to be removed and reinserted, which fixes the problem (albeit in a hacky way). It's unfortunate that we need to do a full re-enumeration of devices at wakeup time, but this is better than alternative of letting the bus get wedged. Signed-off-by: Randy Li <ayaka@soulik.info> --- drivers/usb/dwc2/core_intr.c | 11 +++++++++++ 1 file changed, 11 insertions(+)