| Message ID | 1473076452-19795-8-git-send-email-rabin.vincent@axis.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Mon, Sep 05, 2016 at 01:54:11PM +0200, Rabin Vincent wrote: > From: Rabin Vincent <rabinv@axis.com> > > In the CRIS v17 CPU an ADDC (add with carry) instruction has been added > compared to the v10 instruction set. > > Assembler syntax: > > ADDC [Rs],Rd > ADDC [Rs+],Rd > > Size: Dword > > Description: > > The source data is added together with the carry flag to the > destination register. The size of the operation is dword. > > Operation: > > Rd += s + C-flag; > > Flags affected: > > S R P U I X N Z V C > - - - - - 0 * * * * > > Instruction format: ADDC [Rs],Rd > > +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ > |Destination(Rd)| 1 0 0 1 1 0 1 0 | Source(Rs) | > +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ > > Instruction format: ADDC [Rs+],Rd > > +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ > |Destination(Rd)| 1 1 0 1 1 0 1 0 | Source(Rs) | > +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ > > Signed-off-by: Rabin Vincent <rabinv@axis.com> > --- > target-cris/cpu.c | 14 ++++++++++++++ > target-cris/crisv10-decode.h | 1 + > target-cris/translate_v10.c | 8 ++++++++ > 3 files changed, 23 insertions(+) > > diff --git a/target-cris/cpu.c b/target-cris/cpu.c > index c5a656b..d680cfb 100644 > --- a/target-cris/cpu.c > +++ b/target-cris/cpu.c > @@ -246,6 +246,16 @@ static void crisv11_cpu_class_init(ObjectClass *oc, void *data) > cc->gdb_read_register = crisv10_cpu_gdb_read_register; > } > > +static void crisv17_cpu_class_init(ObjectClass *oc, void *data) > +{ > + CPUClass *cc = CPU_CLASS(oc); > + CRISCPUClass *ccc = CRIS_CPU_CLASS(oc); > + > + ccc->vr = 17; > + cc->do_interrupt = crisv10_cpu_do_interrupt; > + cc->gdb_read_register = crisv10_cpu_gdb_read_register; > +} > + > static void crisv32_cpu_class_init(ObjectClass *oc, void *data) > { > CRISCPUClass *ccc = CRIS_CPU_CLASS(oc); > @@ -273,6 +283,10 @@ static const TypeInfo cris_cpu_model_type_infos[] = { > .parent = TYPE_CRIS_CPU, > .class_init = crisv11_cpu_class_init, > }, { > + .name = TYPE("crisv17"), > + .parent = TYPE_CRIS_CPU, > + .class_init = crisv17_cpu_class_init, > + }, { > .name = TYPE("crisv32"), > .parent = TYPE_CRIS_CPU, > .class_init = crisv32_cpu_class_init, > diff --git a/target-cris/crisv10-decode.h b/target-cris/crisv10-decode.h > index 587fbdd..bdb4b6d 100644 > --- a/target-cris/crisv10-decode.h > +++ b/target-cris/crisv10-decode.h > @@ -92,6 +92,7 @@ > #define CRISV10_IND_JUMP_M 4 > #define CRISV10_IND_DIP 5 > #define CRISV10_IND_JUMP_R 6 > +#define CRISV17_IND_ADDC 6 > #define CRISV10_IND_BOUND 7 > #define CRISV10_IND_BCC_M 7 > #define CRISV10_IND_MOVE_M_SPR 8 > diff --git a/target-cris/translate_v10.c b/target-cris/translate_v10.c > index a3da425..33d86eb 100644 > --- a/target-cris/translate_v10.c > +++ b/target-cris/translate_v10.c > @@ -1097,6 +1097,14 @@ static unsigned int dec10_ind(CPUCRISState *env, DisasContext *dc) > insn_len = dec10_bdap_m(env, dc, size); > break; > default: > + if (dc->opcode == CRISV17_IND_ADDC && dc->size == 2 && > + env->pregs[PR_VR] == 17) { Hi Rabin, Could you please add some comments on the insn encoding? Put the stuff from the commit msg in here. IIRC, ADDC and v17 are modifications made to the CRISv10 family of cores that never made it into the public manuals. Or am I wrong? Cheers, Edgar > + LOG_DIS("addc op=%d %d\n", dc->src, dc->dst); > + cris_cc_mask(dc, CC_MASK_NZVC); > + insn_len += dec10_ind_alu(env, dc, CC_OP_ADDC, size); > + break; > + } > + > LOG_DIS("pc=%x var-ind.%d %d r%d r%d\n", > dc->pc, size, dc->opcode, dc->src, dc->dst); > cpu_abort(CPU(dc->cpu), "Unhandled opcode"); > -- > 2.1.4 >
diff --git a/target-cris/cpu.c b/target-cris/cpu.c index c5a656b..d680cfb 100644 --- a/target-cris/cpu.c +++ b/target-cris/cpu.c @@ -246,6 +246,16 @@ static void crisv11_cpu_class_init(ObjectClass *oc, void *data) cc->gdb_read_register = crisv10_cpu_gdb_read_register; } +static void crisv17_cpu_class_init(ObjectClass *oc, void *data) +{ + CPUClass *cc = CPU_CLASS(oc); + CRISCPUClass *ccc = CRIS_CPU_CLASS(oc); + + ccc->vr = 17; + cc->do_interrupt = crisv10_cpu_do_interrupt; + cc->gdb_read_register = crisv10_cpu_gdb_read_register; +} + static void crisv32_cpu_class_init(ObjectClass *oc, void *data) { CRISCPUClass *ccc = CRIS_CPU_CLASS(oc); @@ -273,6 +283,10 @@ static const TypeInfo cris_cpu_model_type_infos[] = { .parent = TYPE_CRIS_CPU, .class_init = crisv11_cpu_class_init, }, { + .name = TYPE("crisv17"), + .parent = TYPE_CRIS_CPU, + .class_init = crisv17_cpu_class_init, + }, { .name = TYPE("crisv32"), .parent = TYPE_CRIS_CPU, .class_init = crisv32_cpu_class_init, diff --git a/target-cris/crisv10-decode.h b/target-cris/crisv10-decode.h index 587fbdd..bdb4b6d 100644 --- a/target-cris/crisv10-decode.h +++ b/target-cris/crisv10-decode.h @@ -92,6 +92,7 @@ #define CRISV10_IND_JUMP_M 4 #define CRISV10_IND_DIP 5 #define CRISV10_IND_JUMP_R 6 +#define CRISV17_IND_ADDC 6 #define CRISV10_IND_BOUND 7 #define CRISV10_IND_BCC_M 7 #define CRISV10_IND_MOVE_M_SPR 8 diff --git a/target-cris/translate_v10.c b/target-cris/translate_v10.c index a3da425..33d86eb 100644 --- a/target-cris/translate_v10.c +++ b/target-cris/translate_v10.c @@ -1097,6 +1097,14 @@ static unsigned int dec10_ind(CPUCRISState *env, DisasContext *dc) insn_len = dec10_bdap_m(env, dc, size); break; default: + if (dc->opcode == CRISV17_IND_ADDC && dc->size == 2 && + env->pregs[PR_VR] == 17) { + LOG_DIS("addc op=%d %d\n", dc->src, dc->dst); + cris_cc_mask(dc, CC_MASK_NZVC); + insn_len += dec10_ind_alu(env, dc, CC_OP_ADDC, size); + break; + } + LOG_DIS("pc=%x var-ind.%d %d r%d r%d\n", dc->pc, size, dc->opcode, dc->src, dc->dst); cpu_abort(CPU(dc->cpu), "Unhandled opcode");