diff mbox

[9/9] target-mips: Add EVA support to P5600

Message ID 7b20bd7ef43dd5446780cb80de15643bd5e546fc.1473159543.git-series.james.hogan@imgtec.com (mailing list archive)
State New, archived
Headers show

Commit Message

James Hogan Sept. 6, 2016, 11:03 a.m. UTC 
Add the Enhanced Virtual Addressing (EVA) feature to the P5600 core
configuration, along with the related Segmentation Control (SC) feature
and writable CP0_EBase.WG bit.

This allows it to run Malta EVA kernels.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Leon Alrae <leon.alrae@imgtec.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
---
 target-mips/translate_init.c | 14 ++++++++------
 1 file changed, 8 insertions(+), 6 deletions(-)

Comments

Yongbok Kim Oct. 13, 2016, 1:15 p.m. UTC | #1 
On 06/09/2016 12:03, James Hogan wrote:
> Add the Enhanced Virtual Addressing (EVA) feature to the P5600 core
> configuration, along with the related Segmentation Control (SC) feature
> and writable CP0_EBase.WG bit.
> 
> This allows it to run Malta EVA kernels.
> 
> Signed-off-by: James Hogan <james.hogan@imgtec.com>
> Cc: Leon Alrae <leon.alrae@imgtec.com>
> Cc: Aurelien Jarno <aurelien@aurel32.net>
> ---
>  target-mips/translate_init.c | 14 ++++++++------
>  1 file changed, 8 insertions(+), 6 deletions(-)
> 
> diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
> index f327e6e7de6c..58d5d429941a 100644
> --- a/target-mips/translate_init.c
> +++ b/target-mips/translate_init.c
> @@ -399,9 +399,9 @@ static const mips_def_t mips_defs[] =
>      },
>      {
>          /* FIXME:
> -         * Config3: CMGCR, SC, PW, VZ, CTXTC, CDMM, TL
> +         * Config3: CMGCR, PW, VZ, CTXTC, CDMM, TL
>           * Config4: MMUExtDef
> -         * Config5: EVA, MRP
> +         * Config5: MRP
>           * FIR(FCR0): Has2008
>           * */
>          .name = "P5600",
> @@ -414,13 +414,14 @@ static const mips_def_t mips_defs[] =
>                         (1 << CP0C1_PC) | (1 << CP0C1_FP),
>          .CP0_Config2 = MIPS_CONFIG2,
>          .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_MSAP) |
> -                       (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULRI) |
> -                       (1 << CP0C3_RXI) | (1 << CP0C3_LPA) | (1 << CP0C3_VInt),
> +                       (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_SC) |
> +                       (1 << CP0C3_ULRI) | (1 << CP0C3_RXI) | (1 << CP0C3_LPA) |
> +                       (1 << CP0C3_VInt),
>          .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (2 << CP0C4_IE) |
>                         (0x1c << CP0C4_KScrExist),
>          .CP0_Config4_rw_bitmask = 0,
> -        .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_MVH) | (1 << CP0C5_LLB) |
> -                       (1 << CP0C5_MRP),
> +        .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_EVA) | (1 << CP0C5_MVH) |
> +                       (1 << CP0C5_LLB) | (1 << CP0C5_MRP),
>          .CP0_Config5_rw_bitmask = (1 << CP0C5_K) | (1 << CP0C5_CV) |
>                                    (1 << CP0C5_MSAEn) | (1 << CP0C5_UFE) |
>                                    (1 << CP0C5_FRE) | (1 << CP0C5_UFR),
> @@ -431,6 +432,7 @@ static const mips_def_t mips_defs[] =
>          .CP0_Status_rw_bitmask = 0x3C68FF1F,
>          .CP0_PageGrain_rw_bitmask = (1U << CP0PG_RIE) | (1 << CP0PG_XIE) |
>                      (1 << CP0PG_ELPA) | (1 << CP0PG_IEC),
> +        .CP0_EBase_rw_bitmask = (1 << CP0EBase_WG),
>          .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_UFRP) | (1 << FCR0_HAS2008) |
>                      (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
>                      (1 << FCR0_D) | (1 << FCR0_S) | (0x03 << FCR0_PRID),
> 

Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>

Regards,
Yongbok
diff mbox

Patch

diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index f327e6e7de6c..58d5d429941a 100644
--- a/target-mips/translate_init.c
+++ b/target-mips/translate_init.c
@@ -399,9 +399,9 @@  static const mips_def_t mips_defs[] =
     },
     {
         /* FIXME:
-         * Config3: CMGCR, SC, PW, VZ, CTXTC, CDMM, TL
+         * Config3: CMGCR, PW, VZ, CTXTC, CDMM, TL
          * Config4: MMUExtDef
-         * Config5: EVA, MRP
+         * Config5: MRP
          * FIR(FCR0): Has2008
          * */
         .name = "P5600",
@@ -414,13 +414,14 @@  static const mips_def_t mips_defs[] =
                        (1 << CP0C1_PC) | (1 << CP0C1_FP),
         .CP0_Config2 = MIPS_CONFIG2,
         .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_MSAP) |
-                       (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULRI) |
-                       (1 << CP0C3_RXI) | (1 << CP0C3_LPA) | (1 << CP0C3_VInt),
+                       (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_SC) |
+                       (1 << CP0C3_ULRI) | (1 << CP0C3_RXI) | (1 << CP0C3_LPA) |
+                       (1 << CP0C3_VInt),
         .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (2 << CP0C4_IE) |
                        (0x1c << CP0C4_KScrExist),
         .CP0_Config4_rw_bitmask = 0,
-        .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_MVH) | (1 << CP0C5_LLB) |
-                       (1 << CP0C5_MRP),
+        .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_EVA) | (1 << CP0C5_MVH) |
+                       (1 << CP0C5_LLB) | (1 << CP0C5_MRP),
         .CP0_Config5_rw_bitmask = (1 << CP0C5_K) | (1 << CP0C5_CV) |
                                   (1 << CP0C5_MSAEn) | (1 << CP0C5_UFE) |
                                   (1 << CP0C5_FRE) | (1 << CP0C5_UFR),
@@ -431,6 +432,7 @@  static const mips_def_t mips_defs[] =
         .CP0_Status_rw_bitmask = 0x3C68FF1F,
         .CP0_PageGrain_rw_bitmask = (1U << CP0PG_RIE) | (1 << CP0PG_XIE) |
                     (1 << CP0PG_ELPA) | (1 << CP0PG_IEC),
+        .CP0_EBase_rw_bitmask = (1 << CP0EBase_WG),
         .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_UFRP) | (1 << FCR0_HAS2008) |
                     (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
                     (1 << FCR0_D) | (1 << FCR0_S) | (0x03 << FCR0_PRID),