diff mbox

[v1,01/30] target-sparc: ignore MMU-faults if MMU is disabled in hypervisor mode

Message ID 7b3b6f6a47306f204437e46005ed2098545e6c80.1478291230.git.atar4qemu@gmail.com (mailing list archive)
State New, archived
Headers show

Commit Message

Artyom Tarasenko Nov. 4, 2016, 8:50 p.m. UTC
while IMMU/DMMU is disabled
- ignore MMU-faults in hypervisorv mode or if CPU doesn't have hypervisor
- signal TT_INSN_REAL_TRANSLATION_MISS/TT_DATA_REAL_TRANSLATION_MISS otherwise

Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
---
 target-sparc/cpu.h         |  2 ++
 target-sparc/ldst_helper.c | 15 +++++++++++++--
 2 files changed, 15 insertions(+), 2 deletions(-)

Comments

Richard Henderson Nov. 4, 2016, 9:19 p.m. UTC | #1
On 11/04/2016 02:50 PM, Artyom Tarasenko wrote:
> +    if (is_exec) { /* XXX has_hypervisor */
> +        if (env->lsu & (IMMU_E)) {
> +            cpu_raise_exception_ra(env, TT_CODE_ACCESS, GETPC());
> +        } else if (cpu_has_hypervisor(env) && !(env->hpstate & HS_PRIV)) {
> +            cpu_raise_exception_ra(env, TT_INSN_REAL_TRANSLATION_MISS, GETPC());
> +        }
> +    } else {
> +        if (env->lsu & (DMMU_E)) {
> +            cpu_raise_exception_ra(env, TT_DATA_ACCESS, GETPC());
> +        } else if (cpu_has_hypervisor(env) && !(env->hpstate & HS_PRIV)) {
> +            cpu_raise_exception_ra(env, TT_DATA_REAL_TRANSLATION_MISS, GETPC());
> +        }
> +    }

And if the hypervisor itself has a bug and references bad memory?  Or does the 
hypervisor *have* to do such things in order to probe for device on startup, 
and should therefore not trap.

I'm actually assuming this is the case based on the fact that you wrote this 
patch in the first place.  But if so, we need a comment here.


r~
Artyom Tarasenko Nov. 5, 2016, 9:20 p.m. UTC | #2
On Fri, Nov 4, 2016 at 10:19 PM, Richard Henderson <rth@twiddle.net> wrote:
> On 11/04/2016 02:50 PM, Artyom Tarasenko wrote:
>>
>> +    if (is_exec) { /* XXX has_hypervisor */
>> +        if (env->lsu & (IMMU_E)) {
>> +            cpu_raise_exception_ra(env, TT_CODE_ACCESS, GETPC());
>> +        } else if (cpu_has_hypervisor(env) && !(env->hpstate & HS_PRIV))
>> {
>> +            cpu_raise_exception_ra(env, TT_INSN_REAL_TRANSLATION_MISS,
>> GETPC());
>> +        }
>> +    } else {
>> +        if (env->lsu & (DMMU_E)) {
>> +            cpu_raise_exception_ra(env, TT_DATA_ACCESS, GETPC());
>> +        } else if (cpu_has_hypervisor(env) && !(env->hpstate & HS_PRIV))
>> {
>> +            cpu_raise_exception_ra(env, TT_DATA_REAL_TRANSLATION_MISS,
>> GETPC());
>> +        }
>> +    }
>
>
> And if the hypervisor itself has a bug and references bad memory?

The MMU is usually switched on. The exception is the early initialization.

> Or does
> the hypervisor *have* to do such things in order to probe for device on
> startup, and should therefore not trap.
>
> I'm actually assuming this is the case based on the fact that you wrote this
> patch in the first place.

Yep.

> But if so, we need a comment here.

With MMU switched off there is no circuit which would produce a MMU fault.
Neither under sun4v nor under sun4u. Do we really have to document it?

Btw it works the same way under sun4m just 26 lines above.
diff mbox

Patch

diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
index 5fb0ed1..e0b2806 100644
--- a/target-sparc/cpu.h
+++ b/target-sparc/cpu.h
@@ -68,6 +68,8 @@ 
 #define TT_DATA_ACCESS 0x32
 #define TT_UNALIGNED 0x34
 #define TT_PRIV_ACT 0x37
+#define TT_INSN_REAL_TRANSLATION_MISS 0x3e
+#define TT_DATA_REAL_TRANSLATION_MISS 0x3f
 #define TT_EXTINT   0x40
 #define TT_IVEC     0x60
 #define TT_TMISS    0x64
diff --git a/target-sparc/ldst_helper.c b/target-sparc/ldst_helper.c
index de7d53a..fdca87f 100644
--- a/target-sparc/ldst_helper.c
+++ b/target-sparc/ldst_helper.c
@@ -1664,14 +1664,25 @@  void sparc_cpu_unassigned_access(CPUState *cs, hwaddr addr,
 {
     SPARCCPU *cpu = SPARC_CPU(cs);
     CPUSPARCState *env = &cpu->env;
-    int tt = is_exec ? TT_CODE_ACCESS : TT_DATA_ACCESS;
 
 #ifdef DEBUG_UNASSIGNED
     printf("Unassigned mem access to " TARGET_FMT_plx " from " TARGET_FMT_lx
            "\n", addr, env->pc);
 #endif
 
-    cpu_raise_exception_ra(env, tt, GETPC());
+    if (is_exec) { /* XXX has_hypervisor */
+        if (env->lsu & (IMMU_E)) {
+            cpu_raise_exception_ra(env, TT_CODE_ACCESS, GETPC());
+        } else if (cpu_has_hypervisor(env) && !(env->hpstate & HS_PRIV)) {
+            cpu_raise_exception_ra(env, TT_INSN_REAL_TRANSLATION_MISS, GETPC());
+        }
+    } else {
+        if (env->lsu & (DMMU_E)) {
+            cpu_raise_exception_ra(env, TT_DATA_ACCESS, GETPC());
+        } else if (cpu_has_hypervisor(env) && !(env->hpstate & HS_PRIV)) {
+            cpu_raise_exception_ra(env, TT_DATA_REAL_TRANSLATION_MISS, GETPC());
+        }
+    }
 }
 #endif
 #endif