diff mbox

[v2,4/5] drm/i915: Pass dev_priv to INTEL_INFO everywhere apart from the gen use

Message ID 1478691045-18433-1-git-send-email-tvrtko.ursulin@linux.intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Tvrtko Ursulin Nov. 9, 2016, 11:30 a.m. UTC 
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

After this patch only conversion of INTEL_INFO(p)->gen to
INTEL_GEN(dev_priv) remains before the __I915__ macro can
be removed.

v2: Tidy vlv_compute_wm. (David Weinehall)

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: David Weinehall <david.weinehall@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c      |  4 ++--
 drivers/gpu/drm/i915/i915_gem_gtt.c  |  2 +-
 drivers/gpu/drm/i915/intel_color.c   | 31 ++++++++++++++-----------------
 drivers/gpu/drm/i915/intel_display.c | 28 +++++++++++++---------------
 drivers/gpu/drm/i915/intel_fbdev.c   | 10 +++++-----
 drivers/gpu/drm/i915/intel_pm.c      | 12 +++++++-----
 6 files changed, 42 insertions(+), 45 deletions(-)

Comments

David Weinehall Nov. 9, 2016, 11:42 a.m. UTC | #1 
On Wed, Nov 09, 2016 at 11:30:45AM +0000, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> After this patch only conversion of INTEL_INFO(p)->gen to
> INTEL_GEN(dev_priv) remains before the __I915__ macro can
> be removed.
> 
> v2: Tidy vlv_compute_wm. (David Weinehall)
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: David Weinehall <david.weinehall@linux.intel.com>

Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/i915_drv.c      |  4 ++--
>  drivers/gpu/drm/i915/i915_gem_gtt.c  |  2 +-
>  drivers/gpu/drm/i915/intel_color.c   | 31 ++++++++++++++-----------------
>  drivers/gpu/drm/i915/intel_display.c | 28 +++++++++++++---------------
>  drivers/gpu/drm/i915/intel_fbdev.c   | 10 +++++-----
>  drivers/gpu/drm/i915/intel_pm.c      | 12 +++++++-----
>  6 files changed, 42 insertions(+), 45 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 0213a3090ab3..20b1e19d982b 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -150,7 +150,7 @@ static void intel_detect_pch(struct drm_device *dev)
>  	/* In all current cases, num_pipes is equivalent to the PCH_NOP setting
>  	 * (which really amounts to a PCH but no South Display).
>  	 */
> -	if (INTEL_INFO(dev)->num_pipes == 0) {
> +	if (INTEL_INFO(dev_priv)->num_pipes == 0) {
>  		dev_priv->pch_type = PCH_NOP;
>  		return;
>  	}
> @@ -607,7 +607,7 @@ static int i915_load_modeset_init(struct drm_device *dev)
>  
>  	intel_modeset_gem_init(dev);
>  
> -	if (INTEL_INFO(dev)->num_pipes == 0)
> +	if (INTEL_INFO(dev_priv)->num_pipes == 0)
>  		return 0;
>  
>  	ret = intel_fbdev_init(dev);
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index a5fafa3d4fc8..2eb22ba06bc0 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -714,7 +714,7 @@ static int gen8_48b_mm_switch(struct i915_hw_ppgtt *ppgtt,
>   */
>  static void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt)
>  {
> -	ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->base.dev)->ring_mask;
> +	ppgtt->pd_dirty_rings = INTEL_INFO(to_i915(ppgtt->base.dev))->ring_mask;
>  }
>  
>  /* Removes entries from a single page table, releasing it if it's empty.
> diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
> index 445108855275..3784940a4e7a 100644
> --- a/drivers/gpu/drm/i915/intel_color.c
> +++ b/drivers/gpu/drm/i915/intel_color.c
> @@ -345,11 +345,10 @@ static void haswell_load_luts(struct drm_crtc_state *crtc_state)
>  static void broadwell_load_luts(struct drm_crtc_state *state)
>  {
>  	struct drm_crtc *crtc = state->crtc;
> -	struct drm_device *dev = crtc->dev;
> -	struct drm_i915_private *dev_priv = to_i915(dev);
> +	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
>  	struct intel_crtc_state *intel_state = to_intel_crtc_state(state);
>  	enum pipe pipe = to_intel_crtc(crtc)->pipe;
> -	uint32_t i, lut_size = INTEL_INFO(dev)->color.degamma_lut_size;
> +	uint32_t i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
>  
>  	if (crtc_state_is_legacy(state)) {
>  		haswell_load_luts(state);
> @@ -428,8 +427,7 @@ static void broadwell_load_luts(struct drm_crtc_state *state)
>  static void cherryview_load_luts(struct drm_crtc_state *state)
>  {
>  	struct drm_crtc *crtc = state->crtc;
> -	struct drm_device *dev = crtc->dev;
> -	struct drm_i915_private *dev_priv = to_i915(dev);
> +	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
>  	enum pipe pipe = to_intel_crtc(crtc)->pipe;
>  	struct drm_color_lut *lut;
>  	uint32_t i, lut_size;
> @@ -446,7 +444,7 @@ static void cherryview_load_luts(struct drm_crtc_state *state)
>  
>  	if (state->degamma_lut) {
>  		lut = (struct drm_color_lut *) state->degamma_lut->data;
> -		lut_size = INTEL_INFO(dev)->color.degamma_lut_size;
> +		lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
>  		for (i = 0; i < lut_size; i++) {
>  			/* Write LUT in U0.14 format. */
>  			word0 =
> @@ -461,7 +459,7 @@ static void cherryview_load_luts(struct drm_crtc_state *state)
>  
>  	if (state->gamma_lut) {
>  		lut = (struct drm_color_lut *) state->gamma_lut->data;
> -		lut_size = INTEL_INFO(dev)->color.gamma_lut_size;
> +		lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
>  		for (i = 0; i < lut_size; i++) {
>  			/* Write LUT in U0.10 format. */
>  			word0 =
> @@ -497,12 +495,12 @@ void intel_color_load_luts(struct drm_crtc_state *crtc_state)
>  int intel_color_check(struct drm_crtc *crtc,
>  		      struct drm_crtc_state *crtc_state)
>  {
> -	struct drm_device *dev = crtc->dev;
> +	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
>  	size_t gamma_length, degamma_length;
>  
> -	degamma_length = INTEL_INFO(dev)->color.degamma_lut_size *
> +	degamma_length = INTEL_INFO(dev_priv)->color.degamma_lut_size *
>  		sizeof(struct drm_color_lut);
> -	gamma_length = INTEL_INFO(dev)->color.gamma_lut_size *
> +	gamma_length = INTEL_INFO(dev_priv)->color.gamma_lut_size *
>  		sizeof(struct drm_color_lut);
>  
>  	/*
> @@ -529,8 +527,7 @@ int intel_color_check(struct drm_crtc *crtc,
>  
>  void intel_color_init(struct drm_crtc *crtc)
>  {
> -	struct drm_device *dev = crtc->dev;
> -	struct drm_i915_private *dev_priv = to_i915(dev);
> +	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
>  
>  	drm_mode_crtc_set_gamma_size(crtc, 256);
>  
> @@ -549,10 +546,10 @@ void intel_color_init(struct drm_crtc *crtc)
>  	}
>  
>  	/* Enable color management support when we have degamma & gamma LUTs. */
> -	if (INTEL_INFO(dev)->color.degamma_lut_size != 0 &&
> -	    INTEL_INFO(dev)->color.gamma_lut_size != 0)
> +	if (INTEL_INFO(dev_priv)->color.degamma_lut_size != 0 &&
> +	    INTEL_INFO(dev_priv)->color.gamma_lut_size != 0)
>  		drm_crtc_enable_color_mgmt(crtc,
> -					INTEL_INFO(dev)->color.degamma_lut_size,
> -					true,
> -					INTEL_INFO(dev)->color.gamma_lut_size);
> +					   INTEL_INFO(dev_priv)->color.degamma_lut_size,
> +					   true,
> +					   INTEL_INFO(dev_priv)->color.gamma_lut_size);
>  }
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 2a1abf293a35..e0ad0975755e 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -7053,7 +7053,7 @@ static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
>  		}
>  	}
>  
> -	if (INTEL_INFO(dev)->num_pipes == 2)
> +	if (INTEL_INFO(dev_priv)->num_pipes == 2)
>  		return 0;
>  
>  	/* Ivybridge 3 pipe is really complicated */
> @@ -14725,8 +14725,7 @@ intel_prepare_plane_fb(struct drm_plane *plane,
>  {
>  	struct intel_atomic_state *intel_state =
>  		to_intel_atomic_state(new_state->state);
> -	struct drm_device *dev = plane->dev;
> -	struct drm_i915_private *dev_priv = to_i915(dev);
> +	struct drm_i915_private *dev_priv = to_i915(plane->dev);
>  	struct drm_framebuffer *fb = new_state->fb;
>  	struct drm_i915_gem_object *obj = intel_fb_obj(fb);
>  	struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
> @@ -14783,7 +14782,7 @@ intel_prepare_plane_fb(struct drm_plane *plane,
>  	}
>  
>  	if (plane->type == DRM_PLANE_TYPE_CURSOR &&
> -	    INTEL_INFO(dev)->cursor_needs_physical) {
> +	    INTEL_INFO(dev_priv)->cursor_needs_physical) {
>  		int align = IS_I830(dev_priv) ? 16 * 1024 : 256;
>  		ret = i915_gem_object_attach_phys(obj, align);
>  		if (ret) {
> @@ -14816,7 +14815,7 @@ void
>  intel_cleanup_plane_fb(struct drm_plane *plane,
>  		       struct drm_plane_state *old_state)
>  {
> -	struct drm_device *dev = plane->dev;
> +	struct drm_i915_private *dev_priv = to_i915(plane->dev);
>  	struct intel_plane_state *old_intel_state;
>  	struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
>  	struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
> @@ -14827,7 +14826,7 @@ intel_cleanup_plane_fb(struct drm_plane *plane,
>  		return;
>  
>  	if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
> -	    !INTEL_INFO(dev)->cursor_needs_physical))
> +	    !INTEL_INFO(dev_priv)->cursor_needs_physical))
>  		intel_unpin_fb_obj(old_state->fb, old_state->rotation);
>  }
>  
> @@ -15152,13 +15151,13 @@ intel_update_cursor_plane(struct drm_plane *plane,
>  {
>  	struct drm_crtc *crtc = crtc_state->base.crtc;
>  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> -	struct drm_device *dev = plane->dev;
> +	struct drm_i915_private *dev_priv = to_i915(plane->dev);
>  	struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
>  	uint32_t addr;
>  
>  	if (!obj)
>  		addr = 0;
> -	else if (!INTEL_INFO(dev)->cursor_needs_physical)
> +	else if (!INTEL_INFO(dev_priv)->cursor_needs_physical)
>  		addr = i915_gem_object_ggtt_offset(obj, NULL);
>  	else
>  		addr = obj->phys_handle->busaddr;
> @@ -16440,7 +16439,7 @@ int intel_modeset_init(struct drm_device *dev)
>  
>  	intel_init_pm(dev_priv);
>  
> -	if (INTEL_INFO(dev)->num_pipes == 0)
> +	if (INTEL_INFO(dev_priv)->num_pipes == 0)
>  		return 0;
>  
>  	/*
> @@ -16486,8 +16485,8 @@ int intel_modeset_init(struct drm_device *dev)
>  	dev->mode_config.fb_base = ggtt->mappable_base;
>  
>  	DRM_DEBUG_KMS("%d display pipe%s available.\n",
> -		      INTEL_INFO(dev)->num_pipes,
> -		      INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
> +		      INTEL_INFO(dev_priv)->num_pipes,
> +		      INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : "");
>  
>  	for_each_pipe(dev_priv, pipe) {
>  		int ret;
> @@ -16575,11 +16574,10 @@ static void intel_enable_pipe_a(struct drm_device *dev)
>  static bool
>  intel_check_plane_mapping(struct intel_crtc *crtc)
>  {
> -	struct drm_device *dev = crtc->base.dev;
> -	struct drm_i915_private *dev_priv = to_i915(dev);
> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	u32 val;
>  
> -	if (INTEL_INFO(dev)->num_pipes == 1)
> +	if (INTEL_INFO(dev_priv)->num_pipes == 1)
>  		return true;
>  
>  	val = I915_READ(DSPCNTR(!crtc->plane));
> @@ -17332,7 +17330,7 @@ intel_display_print_error_state(struct drm_i915_error_state_buf *m,
>  	if (!error)
>  		return;
>  
> -	err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
> +	err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev_priv)->num_pipes);
>  	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
>  		err_printf(m, "PWR_WELL_CTL2: %08x\n",
>  			   error->power_well_driver);
> diff --git a/drivers/gpu/drm/i915/intel_fbdev.c b/drivers/gpu/drm/i915/intel_fbdev.c
> index b7098f98bb67..e3cf655bec3b 100644
> --- a/drivers/gpu/drm/i915/intel_fbdev.c
> +++ b/drivers/gpu/drm/i915/intel_fbdev.c
> @@ -359,7 +359,7 @@ static bool intel_fb_initial_config(struct drm_fb_helper *fb_helper,
>  				    struct drm_fb_offset *offsets,
>  				    bool *enabled, int width, int height)
>  {
> -	struct drm_device *dev = fb_helper->dev;
> +	struct drm_i915_private *dev_priv = to_i915(fb_helper->dev);
>  	unsigned long conn_configured, mask;
>  	unsigned int count = min(fb_helper->connector_count, BITS_PER_LONG);
>  	int i, j;
> @@ -512,7 +512,7 @@ static bool intel_fb_initial_config(struct drm_fb_helper *fb_helper,
>  	 * fbdev helper library.
>  	 */
>  	if (num_connectors_enabled != num_connectors_detected &&
> -	    num_connectors_enabled < INTEL_INFO(dev)->num_pipes) {
> +	    num_connectors_enabled < INTEL_INFO(dev_priv)->num_pipes) {
>  		DRM_DEBUG_KMS("fallback: Not all outputs enabled\n");
>  		DRM_DEBUG_KMS("Enabled: %i, detected: %i\n", num_connectors_enabled,
>  			      num_connectors_detected);
> @@ -700,11 +700,11 @@ static void intel_fbdev_suspend_worker(struct work_struct *work)
>  
>  int intel_fbdev_init(struct drm_device *dev)
>  {
> -	struct intel_fbdev *ifbdev;
>  	struct drm_i915_private *dev_priv = to_i915(dev);
> +	struct intel_fbdev *ifbdev;
>  	int ret;
>  
> -	if (WARN_ON(INTEL_INFO(dev)->num_pipes == 0))
> +	if (WARN_ON(INTEL_INFO(dev_priv)->num_pipes == 0))
>  		return -ENODEV;
>  
>  	ifbdev = kzalloc(sizeof(struct intel_fbdev), GFP_KERNEL);
> @@ -717,7 +717,7 @@ int intel_fbdev_init(struct drm_device *dev)
>  		ifbdev->preferred_bpp = 32;
>  
>  	ret = drm_fb_helper_init(dev, &ifbdev->helper,
> -				 INTEL_INFO(dev)->num_pipes, 4);
> +				 INTEL_INFO(dev_priv)->num_pipes, 4);
>  	if (ret) {
>  		kfree(ifbdev);
>  		return ret;
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 88e28c989b9c..368f801aee0f 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -1061,7 +1061,8 @@ static void vlv_invert_wms(struct intel_crtc *crtc)
>  
>  	for (level = 0; level < wm_state->num_levels; level++) {
>  		struct drm_device *dev = crtc->base.dev;
> -		const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
> +		const int sr_fifo_size =
> +			INTEL_INFO(to_i915(dev))->num_pipes * 512 - 1;
>  		struct intel_plane *plane;
>  
>  		wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
> @@ -1091,15 +1092,16 @@ static void vlv_invert_wms(struct intel_crtc *crtc)
>  static void vlv_compute_wm(struct intel_crtc *crtc)
>  {
>  	struct drm_device *dev = crtc->base.dev;
> +	struct drm_i915_private *dev_priv = to_i915(dev);
>  	struct vlv_wm_state *wm_state = &crtc->wm_state;
>  	struct intel_plane *plane;
> -	int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
> +	int sr_fifo_size = INTEL_INFO(dev_priv)->num_pipes * 512 - 1;
>  	int level;
>  
>  	memset(wm_state, 0, sizeof(*wm_state));
>  
>  	wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
> -	wm_state->num_levels = to_i915(dev)->wm.max_level + 1;
> +	wm_state->num_levels = dev_priv->wm.max_level + 1;
>  
>  	wm_state->num_active_planes = 0;
>  
> @@ -1179,7 +1181,7 @@ static void vlv_compute_wm(struct intel_crtc *crtc)
>  	}
>  
>  	/* clear any (partially) filled invalid levels */
> -	for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) {
> +	for (level = wm_state->num_levels; level < dev_priv->wm.max_level + 1; level++) {
>  		memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
>  		memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
>  	}
> @@ -1920,7 +1922,7 @@ static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
>  
>  	/* HSW allows LP1+ watermarks even with multiple pipes */
>  	if (level == 0 || config->num_pipes_active > 1) {
> -		fifo_size /= INTEL_INFO(dev)->num_pipes;
> +		fifo_size /= INTEL_INFO(to_i915(dev))->num_pipes;
>  
>  		/*
>  		 * For some reason the non self refresh
> -- 
> 2.7.4
>
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 0213a3090ab3..20b1e19d982b 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -150,7 +150,7 @@  static void intel_detect_pch(struct drm_device *dev)
 	/* In all current cases, num_pipes is equivalent to the PCH_NOP setting
 	 * (which really amounts to a PCH but no South Display).
 	 */
-	if (INTEL_INFO(dev)->num_pipes == 0) {
+	if (INTEL_INFO(dev_priv)->num_pipes == 0) {
 		dev_priv->pch_type = PCH_NOP;
 		return;
 	}
@@ -607,7 +607,7 @@  static int i915_load_modeset_init(struct drm_device *dev)
 
 	intel_modeset_gem_init(dev);
 
-	if (INTEL_INFO(dev)->num_pipes == 0)
+	if (INTEL_INFO(dev_priv)->num_pipes == 0)
 		return 0;
 
 	ret = intel_fbdev_init(dev);
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index a5fafa3d4fc8..2eb22ba06bc0 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -714,7 +714,7 @@  static int gen8_48b_mm_switch(struct i915_hw_ppgtt *ppgtt,
  */
 static void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt)
 {
-	ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->base.dev)->ring_mask;
+	ppgtt->pd_dirty_rings = INTEL_INFO(to_i915(ppgtt->base.dev))->ring_mask;
 }
 
 /* Removes entries from a single page table, releasing it if it's empty.
diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index 445108855275..3784940a4e7a 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -345,11 +345,10 @@  static void haswell_load_luts(struct drm_crtc_state *crtc_state)
 static void broadwell_load_luts(struct drm_crtc_state *state)
 {
 	struct drm_crtc *crtc = state->crtc;
-	struct drm_device *dev = crtc->dev;
-	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
 	struct intel_crtc_state *intel_state = to_intel_crtc_state(state);
 	enum pipe pipe = to_intel_crtc(crtc)->pipe;
-	uint32_t i, lut_size = INTEL_INFO(dev)->color.degamma_lut_size;
+	uint32_t i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
 
 	if (crtc_state_is_legacy(state)) {
 		haswell_load_luts(state);
@@ -428,8 +427,7 @@  static void broadwell_load_luts(struct drm_crtc_state *state)
 static void cherryview_load_luts(struct drm_crtc_state *state)
 {
 	struct drm_crtc *crtc = state->crtc;
-	struct drm_device *dev = crtc->dev;
-	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
 	enum pipe pipe = to_intel_crtc(crtc)->pipe;
 	struct drm_color_lut *lut;
 	uint32_t i, lut_size;
@@ -446,7 +444,7 @@  static void cherryview_load_luts(struct drm_crtc_state *state)
 
 	if (state->degamma_lut) {
 		lut = (struct drm_color_lut *) state->degamma_lut->data;
-		lut_size = INTEL_INFO(dev)->color.degamma_lut_size;
+		lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
 		for (i = 0; i < lut_size; i++) {
 			/* Write LUT in U0.14 format. */
 			word0 =
@@ -461,7 +459,7 @@  static void cherryview_load_luts(struct drm_crtc_state *state)
 
 	if (state->gamma_lut) {
 		lut = (struct drm_color_lut *) state->gamma_lut->data;
-		lut_size = INTEL_INFO(dev)->color.gamma_lut_size;
+		lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
 		for (i = 0; i < lut_size; i++) {
 			/* Write LUT in U0.10 format. */
 			word0 =
@@ -497,12 +495,12 @@  void intel_color_load_luts(struct drm_crtc_state *crtc_state)
 int intel_color_check(struct drm_crtc *crtc,
 		      struct drm_crtc_state *crtc_state)
 {
-	struct drm_device *dev = crtc->dev;
+	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
 	size_t gamma_length, degamma_length;
 
-	degamma_length = INTEL_INFO(dev)->color.degamma_lut_size *
+	degamma_length = INTEL_INFO(dev_priv)->color.degamma_lut_size *
 		sizeof(struct drm_color_lut);
-	gamma_length = INTEL_INFO(dev)->color.gamma_lut_size *
+	gamma_length = INTEL_INFO(dev_priv)->color.gamma_lut_size *
 		sizeof(struct drm_color_lut);
 
 	/*
@@ -529,8 +527,7 @@  int intel_color_check(struct drm_crtc *crtc,
 
 void intel_color_init(struct drm_crtc *crtc)
 {
-	struct drm_device *dev = crtc->dev;
-	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
 
 	drm_mode_crtc_set_gamma_size(crtc, 256);
 
@@ -549,10 +546,10 @@  void intel_color_init(struct drm_crtc *crtc)
 	}
 
 	/* Enable color management support when we have degamma & gamma LUTs. */
-	if (INTEL_INFO(dev)->color.degamma_lut_size != 0 &&
-	    INTEL_INFO(dev)->color.gamma_lut_size != 0)
+	if (INTEL_INFO(dev_priv)->color.degamma_lut_size != 0 &&
+	    INTEL_INFO(dev_priv)->color.gamma_lut_size != 0)
 		drm_crtc_enable_color_mgmt(crtc,
-					INTEL_INFO(dev)->color.degamma_lut_size,
-					true,
-					INTEL_INFO(dev)->color.gamma_lut_size);
+					   INTEL_INFO(dev_priv)->color.degamma_lut_size,
+					   true,
+					   INTEL_INFO(dev_priv)->color.gamma_lut_size);
 }
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 2a1abf293a35..e0ad0975755e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7053,7 +7053,7 @@  static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
 		}
 	}
 
-	if (INTEL_INFO(dev)->num_pipes == 2)
+	if (INTEL_INFO(dev_priv)->num_pipes == 2)
 		return 0;
 
 	/* Ivybridge 3 pipe is really complicated */
@@ -14725,8 +14725,7 @@  intel_prepare_plane_fb(struct drm_plane *plane,
 {
 	struct intel_atomic_state *intel_state =
 		to_intel_atomic_state(new_state->state);
-	struct drm_device *dev = plane->dev;
-	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct drm_i915_private *dev_priv = to_i915(plane->dev);
 	struct drm_framebuffer *fb = new_state->fb;
 	struct drm_i915_gem_object *obj = intel_fb_obj(fb);
 	struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
@@ -14783,7 +14782,7 @@  intel_prepare_plane_fb(struct drm_plane *plane,
 	}
 
 	if (plane->type == DRM_PLANE_TYPE_CURSOR &&
-	    INTEL_INFO(dev)->cursor_needs_physical) {
+	    INTEL_INFO(dev_priv)->cursor_needs_physical) {
 		int align = IS_I830(dev_priv) ? 16 * 1024 : 256;
 		ret = i915_gem_object_attach_phys(obj, align);
 		if (ret) {
@@ -14816,7 +14815,7 @@  void
 intel_cleanup_plane_fb(struct drm_plane *plane,
 		       struct drm_plane_state *old_state)
 {
-	struct drm_device *dev = plane->dev;
+	struct drm_i915_private *dev_priv = to_i915(plane->dev);
 	struct intel_plane_state *old_intel_state;
 	struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
 	struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
@@ -14827,7 +14826,7 @@  intel_cleanup_plane_fb(struct drm_plane *plane,
 		return;
 
 	if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
-	    !INTEL_INFO(dev)->cursor_needs_physical))
+	    !INTEL_INFO(dev_priv)->cursor_needs_physical))
 		intel_unpin_fb_obj(old_state->fb, old_state->rotation);
 }
 
@@ -15152,13 +15151,13 @@  intel_update_cursor_plane(struct drm_plane *plane,
 {
 	struct drm_crtc *crtc = crtc_state->base.crtc;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-	struct drm_device *dev = plane->dev;
+	struct drm_i915_private *dev_priv = to_i915(plane->dev);
 	struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
 	uint32_t addr;
 
 	if (!obj)
 		addr = 0;
-	else if (!INTEL_INFO(dev)->cursor_needs_physical)
+	else if (!INTEL_INFO(dev_priv)->cursor_needs_physical)
 		addr = i915_gem_object_ggtt_offset(obj, NULL);
 	else
 		addr = obj->phys_handle->busaddr;
@@ -16440,7 +16439,7 @@  int intel_modeset_init(struct drm_device *dev)
 
 	intel_init_pm(dev_priv);
 
-	if (INTEL_INFO(dev)->num_pipes == 0)
+	if (INTEL_INFO(dev_priv)->num_pipes == 0)
 		return 0;
 
 	/*
@@ -16486,8 +16485,8 @@  int intel_modeset_init(struct drm_device *dev)
 	dev->mode_config.fb_base = ggtt->mappable_base;
 
 	DRM_DEBUG_KMS("%d display pipe%s available.\n",
-		      INTEL_INFO(dev)->num_pipes,
-		      INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
+		      INTEL_INFO(dev_priv)->num_pipes,
+		      INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : "");
 
 	for_each_pipe(dev_priv, pipe) {
 		int ret;
@@ -16575,11 +16574,10 @@  static void intel_enable_pipe_a(struct drm_device *dev)
 static bool
 intel_check_plane_mapping(struct intel_crtc *crtc)
 {
-	struct drm_device *dev = crtc->base.dev;
-	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	u32 val;
 
-	if (INTEL_INFO(dev)->num_pipes == 1)
+	if (INTEL_INFO(dev_priv)->num_pipes == 1)
 		return true;
 
 	val = I915_READ(DSPCNTR(!crtc->plane));
@@ -17332,7 +17330,7 @@  intel_display_print_error_state(struct drm_i915_error_state_buf *m,
 	if (!error)
 		return;
 
-	err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
+	err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev_priv)->num_pipes);
 	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 		err_printf(m, "PWR_WELL_CTL2: %08x\n",
 			   error->power_well_driver);
diff --git a/drivers/gpu/drm/i915/intel_fbdev.c b/drivers/gpu/drm/i915/intel_fbdev.c
index b7098f98bb67..e3cf655bec3b 100644
--- a/drivers/gpu/drm/i915/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/intel_fbdev.c
@@ -359,7 +359,7 @@  static bool intel_fb_initial_config(struct drm_fb_helper *fb_helper,
 				    struct drm_fb_offset *offsets,
 				    bool *enabled, int width, int height)
 {
-	struct drm_device *dev = fb_helper->dev;
+	struct drm_i915_private *dev_priv = to_i915(fb_helper->dev);
 	unsigned long conn_configured, mask;
 	unsigned int count = min(fb_helper->connector_count, BITS_PER_LONG);
 	int i, j;
@@ -512,7 +512,7 @@  static bool intel_fb_initial_config(struct drm_fb_helper *fb_helper,
 	 * fbdev helper library.
 	 */
 	if (num_connectors_enabled != num_connectors_detected &&
-	    num_connectors_enabled < INTEL_INFO(dev)->num_pipes) {
+	    num_connectors_enabled < INTEL_INFO(dev_priv)->num_pipes) {
 		DRM_DEBUG_KMS("fallback: Not all outputs enabled\n");
 		DRM_DEBUG_KMS("Enabled: %i, detected: %i\n", num_connectors_enabled,
 			      num_connectors_detected);
@@ -700,11 +700,11 @@  static void intel_fbdev_suspend_worker(struct work_struct *work)
 
 int intel_fbdev_init(struct drm_device *dev)
 {
-	struct intel_fbdev *ifbdev;
 	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct intel_fbdev *ifbdev;
 	int ret;
 
-	if (WARN_ON(INTEL_INFO(dev)->num_pipes == 0))
+	if (WARN_ON(INTEL_INFO(dev_priv)->num_pipes == 0))
 		return -ENODEV;
 
 	ifbdev = kzalloc(sizeof(struct intel_fbdev), GFP_KERNEL);
@@ -717,7 +717,7 @@  int intel_fbdev_init(struct drm_device *dev)
 		ifbdev->preferred_bpp = 32;
 
 	ret = drm_fb_helper_init(dev, &ifbdev->helper,
-				 INTEL_INFO(dev)->num_pipes, 4);
+				 INTEL_INFO(dev_priv)->num_pipes, 4);
 	if (ret) {
 		kfree(ifbdev);
 		return ret;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 88e28c989b9c..368f801aee0f 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1061,7 +1061,8 @@  static void vlv_invert_wms(struct intel_crtc *crtc)
 
 	for (level = 0; level < wm_state->num_levels; level++) {
 		struct drm_device *dev = crtc->base.dev;
-		const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
+		const int sr_fifo_size =
+			INTEL_INFO(to_i915(dev))->num_pipes * 512 - 1;
 		struct intel_plane *plane;
 
 		wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
@@ -1091,15 +1092,16 @@  static void vlv_invert_wms(struct intel_crtc *crtc)
 static void vlv_compute_wm(struct intel_crtc *crtc)
 {
 	struct drm_device *dev = crtc->base.dev;
+	struct drm_i915_private *dev_priv = to_i915(dev);
 	struct vlv_wm_state *wm_state = &crtc->wm_state;
 	struct intel_plane *plane;
-	int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
+	int sr_fifo_size = INTEL_INFO(dev_priv)->num_pipes * 512 - 1;
 	int level;
 
 	memset(wm_state, 0, sizeof(*wm_state));
 
 	wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
-	wm_state->num_levels = to_i915(dev)->wm.max_level + 1;
+	wm_state->num_levels = dev_priv->wm.max_level + 1;
 
 	wm_state->num_active_planes = 0;
 
@@ -1179,7 +1181,7 @@  static void vlv_compute_wm(struct intel_crtc *crtc)
 	}
 
 	/* clear any (partially) filled invalid levels */
-	for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) {
+	for (level = wm_state->num_levels; level < dev_priv->wm.max_level + 1; level++) {
 		memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
 		memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
 	}
@@ -1920,7 +1922,7 @@  static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
 
 	/* HSW allows LP1+ watermarks even with multiple pipes */
 	if (level == 0 || config->num_pipes_active > 1) {
-		fifo_size /= INTEL_INFO(dev)->num_pipes;
+		fifo_size /= INTEL_INFO(to_i915(dev))->num_pipes;
 
 		/*
 		 * For some reason the non self refresh