| Message ID | 20161123004204.10851-1-stefan@agner.ch (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Tue, Nov 22, 2016 at 10:42 PM, Stefan Agner <stefan@agner.ch> wrote: > The eLCDIF IP of the i.MX 7 SoC knows multiple clocks and lists them > separately: > > Clock Clock Root Description > apb_clk MAIN_AXI_CLK_ROOT AXI clock > pix_clk LCDIF_PIXEL_CLK_ROOT Pixel clock > ipg_clk_s MAIN_AXI_CLK_ROOT Peripheral access clock > > All of them are switched by a single gate, which is part of the > IMX7D_LCDIF_PIXEL_ROOT_CLK clock. Hence using that clock also for > the AXI bus clock (clock-name "axi") makes sure the gate gets > enabled when accessing registers. > > There seem to be no separate AXI display clock, and the clock is > optional. Hence remove the dummy clock. > > This fixes kernel freezes when starting the X-Server (which > disables/re-enables the display controller). > > Signed-off-by: Stefan Agner <stefan@agner.ch> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Hi Shawn On 2016-11-23 15:02, Fabio Estevam wrote: > On Tue, Nov 22, 2016 at 10:42 PM, Stefan Agner <stefan@agner.ch> wrote: >> The eLCDIF IP of the i.MX 7 SoC knows multiple clocks and lists them >> separately: >> >> Clock Clock Root Description >> apb_clk MAIN_AXI_CLK_ROOT AXI clock >> pix_clk LCDIF_PIXEL_CLK_ROOT Pixel clock >> ipg_clk_s MAIN_AXI_CLK_ROOT Peripheral access clock >> >> All of them are switched by a single gate, which is part of the >> IMX7D_LCDIF_PIXEL_ROOT_CLK clock. Hence using that clock also for >> the AXI bus clock (clock-name "axi") makes sure the gate gets >> enabled when accessing registers. >> >> There seem to be no separate AXI display clock, and the clock is >> optional. Hence remove the dummy clock. >> >> This fixes kernel freezes when starting the X-Server (which >> disables/re-enables the display controller). >> >> Signed-off-by: Stefan Agner <stefan@agner.ch> > > Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Since this fixes a kernel freeze, is there a chance to get this still in 4.9? -- Stefan
Hi Arnd, Olof, On Sun, Dec 04, 2016 at 05:26:58PM -0800, Stefan Agner wrote: > Hi Shawn > > On 2016-11-23 15:02, Fabio Estevam wrote: > > On Tue, Nov 22, 2016 at 10:42 PM, Stefan Agner <stefan@agner.ch> wrote: > >> The eLCDIF IP of the i.MX 7 SoC knows multiple clocks and lists them > >> separately: > >> > >> Clock Clock Root Description > >> apb_clk MAIN_AXI_CLK_ROOT AXI clock > >> pix_clk LCDIF_PIXEL_CLK_ROOT Pixel clock > >> ipg_clk_s MAIN_AXI_CLK_ROOT Peripheral access clock > >> > >> All of them are switched by a single gate, which is part of the > >> IMX7D_LCDIF_PIXEL_ROOT_CLK clock. Hence using that clock also for > >> the AXI bus clock (clock-name "axi") makes sure the gate gets > >> enabled when accessing registers. > >> > >> There seem to be no separate AXI display clock, and the clock is > >> optional. Hence remove the dummy clock. > >> > >> This fixes kernel freezes when starting the X-Server (which > >> disables/re-enables the display controller). > >> > >> Signed-off-by: Stefan Agner <stefan@agner.ch> > > > > Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> > > Since this fixes a kernel freeze, is there a chance to get this still in > 4.9? Since we get one more week to the final 4.9, is it possible for you to send this fix for 4.9 inclusion? Thanks. For the patch, Acked-by: Shawn Guo <shawnguo@kernel.org> Shawn
Hello Stefan, On Sun, Dec 04, 2016 at 05:26:58PM -0800, Stefan Agner wrote: > Since this fixes a kernel freeze, is there a chance to get this still in > 4.9? a Fixes:-Line would be nice then. Best regards Uwe
On 2016-12-04 23:06, Uwe Kleine-König wrote: > Hello Stefan, > > On Sun, Dec 04, 2016 at 05:26:58PM -0800, Stefan Agner wrote: >> Since this fixes a kernel freeze, is there a chance to get this still in >> 4.9? > > a Fixes:-Line would be nice then. Good point. Fixes: e8ed73f691bd ("ARM: dts: imx7d: add lcdif support") -- Stefan
On Mon, Dec 05, 2016 at 10:01:24AM +0800, Shawn Guo wrote: > Hi Arnd, Olof, > > On Sun, Dec 04, 2016 at 05:26:58PM -0800, Stefan Agner wrote: > > Hi Shawn > > > > On 2016-11-23 15:02, Fabio Estevam wrote: > > > On Tue, Nov 22, 2016 at 10:42 PM, Stefan Agner <stefan@agner.ch> wrote: > > >> The eLCDIF IP of the i.MX 7 SoC knows multiple clocks and lists them > > >> separately: > > >> > > >> Clock Clock Root Description > > >> apb_clk MAIN_AXI_CLK_ROOT AXI clock > > >> pix_clk LCDIF_PIXEL_CLK_ROOT Pixel clock > > >> ipg_clk_s MAIN_AXI_CLK_ROOT Peripheral access clock > > >> > > >> All of them are switched by a single gate, which is part of the > > >> IMX7D_LCDIF_PIXEL_ROOT_CLK clock. Hence using that clock also for > > >> the AXI bus clock (clock-name "axi") makes sure the gate gets > > >> enabled when accessing registers. > > >> > > >> There seem to be no separate AXI display clock, and the clock is > > >> optional. Hence remove the dummy clock. > > >> > > >> This fixes kernel freezes when starting the X-Server (which > > >> disables/re-enables the display controller). > > >> > > >> Signed-off-by: Stefan Agner <stefan@agner.ch> > > > > > > Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> > > > > Since this fixes a kernel freeze, is there a chance to get this still in > > 4.9? > > Since we get one more week to the final 4.9, is it possible for you to > send this fix for 4.9 inclusion? Thanks. > > For the patch, > > Acked-by: Shawn Guo <shawnguo@kernel.org> Applied, with the fixes line. In the future, please email arm@kernel.org too, it's easier to make sure we don't miss it that way. -Olof
On Wed, Dec 07, 2016 at 12:53:14PM -0800, Olof Johansson wrote: > Applied, with the fixes line. In the future, please email arm@kernel.org too, > it's easier to make sure we don't miss it that way. Noted. Thanks, Olof. Shawn
diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi index 0d7d5ac..2b6cb05 100644 --- a/arch/arm/boot/dts/imx7s.dtsi +++ b/arch/arm/boot/dts/imx7s.dtsi @@ -643,9 +643,8 @@ reg = <0x30730000 0x10000>; interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>, - <&clks IMX7D_CLK_DUMMY>, - <&clks IMX7D_CLK_DUMMY>; - clock-names = "pix", "axi", "disp_axi"; + <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>; + clock-names = "pix", "axi"; status = "disabled"; }; };
The eLCDIF IP of the i.MX 7 SoC knows multiple clocks and lists them separately: Clock Clock Root Description apb_clk MAIN_AXI_CLK_ROOT AXI clock pix_clk LCDIF_PIXEL_CLK_ROOT Pixel clock ipg_clk_s MAIN_AXI_CLK_ROOT Peripheral access clock All of them are switched by a single gate, which is part of the IMX7D_LCDIF_PIXEL_ROOT_CLK clock. Hence using that clock also for the AXI bus clock (clock-name "axi") makes sure the gate gets enabled when accessing registers. There seem to be no separate AXI display clock, and the clock is optional. Hence remove the dummy clock. This fixes kernel freezes when starting the X-Server (which disables/re-enables the display controller). Signed-off-by: Stefan Agner <stefan@agner.ch> --- arch/arm/boot/dts/imx7s.dtsi | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-)