| Message ID | 1480653536-5551-3-git-send-email-anup.patel@broadcom.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Fri, Dec 02, 2016 at 10:08:56AM +0530, Anup Patel wrote: > This patch adds device tree bindings document for the FlexRM > ring manager found on Broadcom iProc SoCs. > > Reviewed-by: Ray Jui <ray.jui@broadcom.com> > Reviewed-by: Scott Branden <scott.branden@broadcom.com> > Signed-off-by: Anup Patel <anup.patel@broadcom.com> > --- > .../bindings/mailbox/brcm,iproc-flexrm-mbox.txt | 60 ++++++++++++++++++++++ > 1 file changed, 60 insertions(+) > create mode 100644 Documentation/devicetree/bindings/mailbox/brcm,iproc-flexrm-mbox.txt > > diff --git a/Documentation/devicetree/bindings/mailbox/brcm,iproc-flexrm-mbox.txt b/Documentation/devicetree/bindings/mailbox/brcm,iproc-flexrm-mbox.txt > new file mode 100644 > index 0000000..e81f116 > --- /dev/null > +++ b/Documentation/devicetree/bindings/mailbox/brcm,iproc-flexrm-mbox.txt > @@ -0,0 +1,60 @@ [...] > +Example: > +-------- > +crypto_mbox: mbox@67000000 { > + compatible = "brcm,flexrm-mbox"; > + reg = <0x67000000 0x200000>; > + msi-parent = <&gic_its 0x7f00>; > + #mbox-cells = <3>; > +}; > + > +crypto_client { > + ... > + mboxes = <&crypto_mbox 0 0x1 0xffff>, > + <&crypto_mbox 1 0x1 0xffff>, > + <&crypto_mbox 16 0x1 0xffff>, > + <&crypto_mbox 17 0x1 0xffff>, > + <&crypto_mbox 30 0x1 0xffff>, > + <&crypto_mbox 31 0x1 0xffff>; The FlexRM part looks fine. I still don't understand what this node is. Is this a h/w block or just a list of mailboxes? What determines the mailbox channel numbers here? I need to see what the complete node looks like. Rob
On Fri, Dec 9, 2016 at 11:31 PM, Rob Herring <robh@kernel.org> wrote: > On Fri, Dec 02, 2016 at 10:08:56AM +0530, Anup Patel wrote: >> This patch adds device tree bindings document for the FlexRM >> ring manager found on Broadcom iProc SoCs. >> >> Reviewed-by: Ray Jui <ray.jui@broadcom.com> >> Reviewed-by: Scott Branden <scott.branden@broadcom.com> >> Signed-off-by: Anup Patel <anup.patel@broadcom.com> >> --- >> .../bindings/mailbox/brcm,iproc-flexrm-mbox.txt | 60 ++++++++++++++++++++++ >> 1 file changed, 60 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/mailbox/brcm,iproc-flexrm-mbox.txt >> >> diff --git a/Documentation/devicetree/bindings/mailbox/brcm,iproc-flexrm-mbox.txt b/Documentation/devicetree/bindings/mailbox/brcm,iproc-flexrm-mbox.txt >> new file mode 100644 >> index 0000000..e81f116 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/mailbox/brcm,iproc-flexrm-mbox.txt >> @@ -0,0 +1,60 @@ > > [...] > >> +Example: >> +-------- >> +crypto_mbox: mbox@67000000 { >> + compatible = "brcm,flexrm-mbox"; >> + reg = <0x67000000 0x200000>; >> + msi-parent = <&gic_its 0x7f00>; >> + #mbox-cells = <3>; >> +}; >> + >> +crypto_client { >> + ... >> + mboxes = <&crypto_mbox 0 0x1 0xffff>, >> + <&crypto_mbox 1 0x1 0xffff>, >> + <&crypto_mbox 16 0x1 0xffff>, >> + <&crypto_mbox 17 0x1 0xffff>, >> + <&crypto_mbox 30 0x1 0xffff>, >> + <&crypto_mbox 31 0x1 0xffff>; > > The FlexRM part looks fine. I still don't understand what this node is. > Is this a h/w block or just a list of mailboxes? What determines the > mailbox channel numbers here? I need to see what the complete node looks > like. The crypto_client is an example mailbox client for FlexRM mailbox. The example shows that we have FlexRM ring manager providing ring based programming interface to Crypto offload engine. The Crypto offload engine driver is a mailbox client driver. FlexRM mailbox requires 3 cells to specify each mailbox channel in "mboxes" attribute of mailbox client DT node. The 1st cell is mailbox channel number (or FlexRM ring number). Rest of the cells are explained in bindings document. Complete node would look something like below: crypto_client { compatible = "brcm,iproc-spu2"; mboxes = <&crypto_mbox 0 0x1 0xffff>, <&crypto_mbox 1 0x1 0xffff>, <&crypto_mbox 16 0x1 0xffff>, <&crypto_mbox 17 0x1 0xffff>, <&crypto_mbox 30 0x1 0xffff>, <&crypto_mbox 31 0x1 0xffff>; }; The Crypto driver was recently submitted by Rob Rice. Refer https://www.spinics.net/lists/kernel/msg2395306.html Similar to Crypto offload engine, we also have RAID offload engine. The RAID offload engine driver is also implemented as mailbox client driver. Regards, Anup
diff --git a/Documentation/devicetree/bindings/mailbox/brcm,iproc-flexrm-mbox.txt b/Documentation/devicetree/bindings/mailbox/brcm,iproc-flexrm-mbox.txt new file mode 100644 index 0000000..e81f116 --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/brcm,iproc-flexrm-mbox.txt @@ -0,0 +1,60 @@ +Broadcom FlexRM Ring Manager +============================ +The Broadcom FlexRM ring manager provides a set of rings which can be +used to submit work to offload engines. An SoC may have multiple FlexRM +hardware blocks. There is one device tree entry per FlexRM block. The +FlexRM driver will create a mailbox-controller instance for given FlexRM +hardware block where each mailbox channel is a separate FlexRM ring. + +Required properties: +-------------------- +- compatible: Should be "brcm,iproc-flexrm-mbox" +- reg: Specifies base physical address and size of the FlexRM + ring registers +- msi-parent: Phandles (and potential Device IDs) to MSI controllers + The FlexRM engine will send MSIs (instead of wired + interrupts) to CPU. There is one MSI for each FlexRM ring. + Refer devicetree/bindings/interrupt-controller/msi.txt +- #mbox-cells: Specifies the number of cells needed to encode a mailbox + channel. This should be 3. + + The 1st cell is the mailbox channel number. + + The 2nd cell contains MSI completion threshold. This is the + number of completion messages for which FlexRM will inject + one MSI interrupt to CPU. + + The 3nd cell contains MSI timer value representing time for + which FlexRM will wait to accumulate N completion messages + where N is the value specified by 2nd cell above. If FlexRM + does not get required number of completion messages in time + specified by this cell then it will inject one MSI interrupt + to CPU provided atleast one completion message is available. + +Optional properties: +-------------------- +- dma-coherent: Present if DMA operations made by the FlexRM engine (such + as DMA descriptor access, access to buffers pointed by DMA + descriptors and read/write pointer updates to DDR) are + cache coherent with the CPU. + +Example: +-------- +crypto_mbox: mbox@67000000 { + compatible = "brcm,flexrm-mbox"; + reg = <0x67000000 0x200000>; + msi-parent = <&gic_its 0x7f00>; + #mbox-cells = <3>; +}; + +crypto_client { + ... + mboxes = <&crypto_mbox 0 0x1 0xffff>, + <&crypto_mbox 1 0x1 0xffff>, + <&crypto_mbox 16 0x1 0xffff>, + <&crypto_mbox 17 0x1 0xffff>, + <&crypto_mbox 30 0x1 0xffff>, + <&crypto_mbox 31 0x1 0xffff>; + }; + ... +};