| Message ID | 20161213152252.53749-3-icenowy@aosc.xyz (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Tue, Dec 13, 2016 at 11:22:48PM +0800, Icenowy Zheng wrote: > The CPUX clock on A33, which is for the Cortex-A7 cores, is designed to > be changeable by changing the rate of PLL_CPUX. > > Add CLK_SET_RATE_PARENT flag to this clock. > > Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Thanks! Maxime
13.12.2016, 23:44, "Maxime Ripard" <maxime.ripard@free-electrons.com>: > On Tue, Dec 13, 2016 at 11:22:48PM +0800, Icenowy Zheng wrote: >> The CPUX clock on A33, which is for the Cortex-A7 cores, is designed to >> be changeable by changing the rate of PLL_CPUX. >> >> Add CLK_SET_RATE_PARENT flag to this clock. >> >> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> > > Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Excuse me, have you merged this patch? If merged, I won't contain it in my PATCH v2, thus the PATCH v2 will contain only an updated OPP patch. > > Thanks! > Maxime > > -- > Maxime Ripard, Free Electrons > Embedded Linux and Kernel engineering > http://free-electrons.com
On Wed, Dec 14, 2016 at 04:54:14AM +0800, Icenowy Zheng wrote: > > > 13.12.2016, 23:44, "Maxime Ripard" <maxime.ripard@free-electrons.com>: > > On Tue, Dec 13, 2016 at 11:22:48PM +0800, Icenowy Zheng wrote: > >> The CPUX clock on A33, which is for the Cortex-A7 cores, is designed to > >> be changeable by changing the rate of PLL_CPUX. > >> > >> Add CLK_SET_RATE_PARENT flag to this clock. > >> > >> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> > > > > Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> > > Excuse me, have you merged this patch? Yes, sorry, that's what I meant :) Maxime
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-a33.c b/drivers/clk/sunxi-ng/ccu-sun8i-a33.c index 0f3e7d2dc19a..0d513d2674cb 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-a33.c +++ b/drivers/clk/sunxi-ng/ccu-sun8i-a33.c @@ -170,7 +170,7 @@ static SUNXI_CCU_N_WITH_GATE_LOCK(pll_ddr1_clk, "pll-ddr1", static const char * const cpux_parents[] = { "osc32k", "osc24M", "pll-cpux" , "pll-cpux" }; static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents, - 0x050, 16, 2, CLK_IS_CRITICAL); + 0x050, 16, 2, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT); static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x050, 0, 2, 0);
The CPUX clock on A33, which is for the Cortex-A7 cores, is designed to be changeable by changing the rate of PLL_CPUX. Add CLK_SET_RATE_PARENT flag to this clock. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> --- drivers/clk/sunxi-ng/ccu-sun8i-a33.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)