| Message ID | 1481307129-29354-1-git-send-email-vathsala.nagaraju@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> On Fri, Dec 09, 2016 at 11:42:09PM +0530, vathsala nagaraju wrote: > For PSR2 , as per spec, PSR2_CTL bit 31 to be set. > for psr1, bit 31 in SRD_CTL to be set. Reporting > "HW Enabled & Active bit" status for psr2 from SRD_CTL > gives wrong status. > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> > Cc: Jim Bride <jim.bride@linux.intel.com> > Signed-off-by: vathsala nagaraju <vathsala.nagaraju@intel.com> > --- > drivers/gpu/drm/i915/i915_debugfs.c | 9 ++++++--- > 1 file changed, 6 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c > index a746130..54e196d 100644 > --- a/drivers/gpu/drm/i915/i915_debugfs.c > +++ b/drivers/gpu/drm/i915/i915_debugfs.c > @@ -2567,9 +2567,12 @@ static int i915_edp_psr_status(struct seq_file *m, void *data) > seq_printf(m, "Re-enable work scheduled: %s\n", > yesno(work_busy(&dev_priv->psr.work.work))); > > - if (HAS_DDI(dev_priv)) > - enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE; > - else { > + if (HAS_DDI(dev_priv)) { > + if (dev_priv->psr.psr2_support) > + enabled = I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE; > + else > + enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE; > + } else { > for_each_pipe(dev_priv, pipe) { > enum transcoder cpu_transcoder = > intel_pipe_to_cpu_transcoder(dev_priv, pipe); > -- > 1.9.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
merged to dinq, thanks for the patch. On Fri, Dec 9, 2016 at 4:39 PM Rodrigo Vivi <rodrigo.vivi@gmail.com> wrote: > > > Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > > On Fri, Dec 09, 2016 at 11:42:09PM +0530, vathsala nagaraju wrote: > > For PSR2 , as per spec, PSR2_CTL bit 31 to be set. > > for psr1, bit 31 in SRD_CTL to be set. Reporting > > "HW Enabled & Active bit" status for psr2 from SRD_CTL > > gives wrong status. > > > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> > > Cc: Jim Bride <jim.bride@linux.intel.com> > > Signed-off-by: vathsala nagaraju <vathsala.nagaraju@intel.com> > > --- > > drivers/gpu/drm/i915/i915_debugfs.c | 9 ++++++--- > > 1 file changed, 6 insertions(+), 3 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c > b/drivers/gpu/drm/i915/i915_debugfs.c > > index a746130..54e196d 100644 > > --- a/drivers/gpu/drm/i915/i915_debugfs.c > > +++ b/drivers/gpu/drm/i915/i915_debugfs.c > > @@ -2567,9 +2567,12 @@ static int i915_edp_psr_status(struct seq_file > *m, void *data) > > seq_printf(m, "Re-enable work scheduled: %s\n", > > yesno(work_busy(&dev_priv->psr.work.work))); > > > > - if (HAS_DDI(dev_priv)) > > - enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE; > > - else { > > + if (HAS_DDI(dev_priv)) { > > + if (dev_priv->psr.psr2_support) > > + enabled = I915_READ(EDP_PSR2_CTL) & > EDP_PSR2_ENABLE; > > + else > > + enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE; > > + } else { > > for_each_pipe(dev_priv, pipe) { > > enum transcoder cpu_transcoder = > > intel_pipe_to_cpu_transcoder(dev_priv, > pipe); > > -- > > 1.9.1 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx >
On Fri, Dec 09, 2016 at 11:42:09PM +0530, vathsala nagaraju wrote: > For PSR2 , as per spec, PSR2_CTL bit 31 to be set. > for psr1, bit 31 in SRD_CTL to be set. Reporting > "HW Enabled & Active bit" status for psr2 from SRD_CTL > gives wrong status. > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> > Cc: Jim Bride <jim.bride@linux.intel.com> > Signed-off-by: vathsala nagaraju <vathsala.nagaraju@intel.com> Reviewed-by: Jim Bride <jim.bride@linux.intel.com> > --- > drivers/gpu/drm/i915/i915_debugfs.c | 9 ++++++--- > 1 file changed, 6 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c > index a746130..54e196d 100644 > --- a/drivers/gpu/drm/i915/i915_debugfs.c > +++ b/drivers/gpu/drm/i915/i915_debugfs.c > @@ -2567,9 +2567,12 @@ static int i915_edp_psr_status(struct seq_file *m, void *data) > seq_printf(m, "Re-enable work scheduled: %s\n", > yesno(work_busy(&dev_priv->psr.work.work))); > > - if (HAS_DDI(dev_priv)) > - enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE; > - else { > + if (HAS_DDI(dev_priv)) { > + if (dev_priv->psr.psr2_support) > + enabled = I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE; > + else > + enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE; > + } else { > for_each_pipe(dev_priv, pipe) { > enum transcoder cpu_transcoder = > intel_pipe_to_cpu_transcoder(dev_priv, pipe); > -- > 1.9.1
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index a746130..54e196d 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -2567,9 +2567,12 @@ static int i915_edp_psr_status(struct seq_file *m, void *data) seq_printf(m, "Re-enable work scheduled: %s\n", yesno(work_busy(&dev_priv->psr.work.work))); - if (HAS_DDI(dev_priv)) - enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE; - else { + if (HAS_DDI(dev_priv)) { + if (dev_priv->psr.psr2_support) + enabled = I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE; + else + enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE; + } else { for_each_pipe(dev_priv, pipe) { enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, pipe);
For PSR2 , as per spec, PSR2_CTL bit 31 to be set. for psr1, bit 31 in SRD_CTL to be set. Reporting "HW Enabled & Active bit" status for psr2 from SRD_CTL gives wrong status. Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Jim Bride <jim.bride@linux.intel.com> Signed-off-by: vathsala nagaraju <vathsala.nagaraju@intel.com> --- drivers/gpu/drm/i915/i915_debugfs.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-)