diff mbox

[RFC,5/6] Documentation: pci: add the exynos5433-pcie binding

Message ID 20161226052029.10552-6-jh80.chung@samsung.com (mailing list archive)
State RFC
Headers show

Commit Message

Jaehoon Chung Dec. 26, 2016, 5:20 a.m. UTC
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
---
 .../devicetree/bindings/pci/exynos5433-pcie.txt    | 36 ++++++++++++++++++++++
 1 file changed, 36 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pci/exynos5433-pcie.txt

Comments

Krzysztof Kozlowski Dec. 27, 2016, 4:19 p.m. UTC | #1
On Mon, Dec 26, 2016 at 02:20:28PM +0900, Jaehoon Chung wrote:
> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
> ---
>  .../devicetree/bindings/pci/exynos5433-pcie.txt    | 36 ++++++++++++++++++++++
>  1 file changed, 36 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/pci/exynos5433-pcie.txt
> 
> diff --git a/Documentation/devicetree/bindings/pci/exynos5433-pcie.txt b/Documentation/devicetree/bindings/pci/exynos5433-pcie.txt
> new file mode 100644
> index 0000000..932a847
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/exynos5433-pcie.txt
> @@ -0,0 +1,36 @@
> +* Samsung Exynos5433 PCIe interface
> +
> +This PCIe host controller is based on the Synopsis Designware PCIe IP

Synopsys.

> +and thus inherits all the common properties defined in designware-pcie.txt.
> +
> +Required properties:
> +- compatible: "samsung,exynos5433-pcie"
> +- reg: base addresses and lengths of the pcie controller,
> +	the phy controller, additional register for the phy controller.

You mentioned three regs but the example contains four of them. Is the
config comming from snps,dw-pcie?

> +- reg-names: Must be "elbi", "phy" and "dbi" for each regs

Again, three here, four in example.

> +- interrupt-names: Must be "intr" for legacy interrupt pin.
> +
> +Other common properites refer to
> +	Documentation/devicetree/binding/pci/designware-pcie.txt
> +
> +Example:
> +
> +	pcie: pcie@15700000 {
> +		compatible ="samsung,exynos5433-pcie", "snps,dw-pcie";
                            ^
			    space needed
> +		#address-cells = <3>;
> +		#size-cells = <2>;
> +		device_type = "pci";
> +		interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
> +		interrupt-names = "intr";
> +		clocks = <&cmu_fsys CLK_PCIE>, <&cmu_fsys CLK_PCLK_PCIE_PHY>;
> +		clock-names = "pcie", "pcie_bus";
> +		num-lanes = <1>;
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pcie_bus>;
> +		reg = <0x156b0000 0x1000>, <0x15680000 0x1000>,
> +		    <0x15700000 0x1000>, <0x0c000000 0x1000>;

Indentation here looks wrong. You indented it with spaces after tabs...
but not to align with line before.

Beside that, fine with me:
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>

Best regards,
Krzysztof


> +		reg-names = "elbi", "phy", "dbi", "config";
> +		ranges = <0x81000000 0 0	  0x0c001000 0 0x00010000
> +			  0x82000000 0 0x0c011000 0x0c011000 0 0x3feefff>;
> +		status = "disabled";
> +	};
> -- 
> 2.10.2
> 
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Jaehoon Chung Dec. 27, 2016, 11:03 p.m. UTC | #2
On 12/28/2016 01:19 AM, Krzysztof Kozlowski wrote:
> On Mon, Dec 26, 2016 at 02:20:28PM +0900, Jaehoon Chung wrote:
>> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
>> ---
>>  .../devicetree/bindings/pci/exynos5433-pcie.txt    | 36 ++++++++++++++++++++++
>>  1 file changed, 36 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/pci/exynos5433-pcie.txt
>>
>> diff --git a/Documentation/devicetree/bindings/pci/exynos5433-pcie.txt b/Documentation/devicetree/bindings/pci/exynos5433-pcie.txt
>> new file mode 100644
>> index 0000000..932a847
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/pci/exynos5433-pcie.txt
>> @@ -0,0 +1,36 @@
>> +* Samsung Exynos5433 PCIe interface
>> +
>> +This PCIe host controller is based on the Synopsis Designware PCIe IP
> 
> Synopsys.

Will fix.

> 
>> +and thus inherits all the common properties defined in designware-pcie.txt.
>> +
>> +Required properties:
>> +- compatible: "samsung,exynos5433-pcie"
>> +- reg: base addresses and lengths of the pcie controller,
>> +	the phy controller, additional register for the phy controller.
> 
> You mentioned three regs but the example contains four of them. Is the
> config comming from snps,dw-pcie?

Oops..It's my mistake. Just needs to put three reg.
Elbi : External local Bus interface register.
Dbi : Data bus interface register.(Control register.)
Config : for configuration space.

"config" can be removed. Because it's not Exynos specific, synopsys's Required property.

> 
>> +- reg-names: Must be "elbi", "phy" and "dbi" for each regs
> 
> Again, three here, four in example.

Will fix.

> 
>> +- interrupt-names: Must be "intr" for legacy interrupt pin.
>> +
>> +Other common properites refer to
>> +	Documentation/devicetree/binding/pci/designware-pcie.txt
>> +
>> +Example:
>> +
>> +	pcie: pcie@15700000 {
>> +		compatible ="samsung,exynos5433-pcie", "snps,dw-pcie";
>                             ^
> 			    space needed
>> +		#address-cells = <3>;
>> +		#size-cells = <2>;
>> +		device_type = "pci";
>> +		interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
>> +		interrupt-names = "intr";
>> +		clocks = <&cmu_fsys CLK_PCIE>, <&cmu_fsys CLK_PCLK_PCIE_PHY>;
>> +		clock-names = "pcie", "pcie_bus";
>> +		num-lanes = <1>;
>> +		pinctrl-names = "default";
>> +		pinctrl-0 = <&pcie_bus>;
>> +		reg = <0x156b0000 0x1000>, <0x15680000 0x1000>,
>> +		    <0x15700000 0x1000>, <0x0c000000 0x1000>;
> 
> Indentation here looks wrong. You indented it with spaces after tabs...
> but not to align with line before.

Will fix.

Best Regards,
Jaehoon Chung

> 
> Beside that, fine with me:
> Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
> 
> Best regards,
> Krzysztof
> 
> 
>> +		reg-names = "elbi", "phy", "dbi", "config";
>> +		ranges = <0x81000000 0 0	  0x0c001000 0 0x00010000
>> +			  0x82000000 0 0x0c011000 0x0c011000 0 0x3feefff>;
>> +		status = "disabled";
>> +	};
>> -- 
>> 2.10.2
>>
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> 
> 
> 

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diff mbox

Patch

diff --git a/Documentation/devicetree/bindings/pci/exynos5433-pcie.txt b/Documentation/devicetree/bindings/pci/exynos5433-pcie.txt
new file mode 100644
index 0000000..932a847
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/exynos5433-pcie.txt
@@ -0,0 +1,36 @@ 
+* Samsung Exynos5433 PCIe interface
+
+This PCIe host controller is based on the Synopsis Designware PCIe IP
+and thus inherits all the common properties defined in designware-pcie.txt.
+
+Required properties:
+- compatible: "samsung,exynos5433-pcie"
+- reg: base addresses and lengths of the pcie controller,
+	the phy controller, additional register for the phy controller.
+- reg-names: Must be "elbi", "phy" and "dbi" for each regs
+- interrupt-names: Must be "intr" for legacy interrupt pin.
+
+Other common properites refer to
+	Documentation/devicetree/binding/pci/designware-pcie.txt
+
+Example:
+
+	pcie: pcie@15700000 {
+		compatible ="samsung,exynos5433-pcie", "snps,dw-pcie";
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "intr";
+		clocks = <&cmu_fsys CLK_PCIE>, <&cmu_fsys CLK_PCLK_PCIE_PHY>;
+		clock-names = "pcie", "pcie_bus";
+		num-lanes = <1>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pcie_bus>;
+		reg = <0x156b0000 0x1000>, <0x15680000 0x1000>,
+		    <0x15700000 0x1000>, <0x0c000000 0x1000>;
+		reg-names = "elbi", "phy", "dbi", "config";
+		ranges = <0x81000000 0 0	  0x0c001000 0 0x00010000
+			  0x82000000 0 0x0c011000 0x0c011000 0 0x3feefff>;
+		status = "disabled";
+	};