| Message ID | 1484216786-17292-7-git-send-email-kishon@ti.com (mailing list archive) |
|---|---|
| State | Not Applicable, archived |
| Delegated to: | Andy Gross |
| Headers | show |
Hi, Às 10:25 AM de 1/12/2017, Kishon Vijay Abraham I escreveu: > No functional change. dw_pcie_cfg_read/dw_pcie_cfg_write doesn't do > anything specific to access configuration space. It can be just renamed > to dw_pcie_read/dw_pcie_write and used to read/write data to dbi space. > This is in preparation for added endpoint support to linux kernel. > > Cc: Jingoo Han <jingoohan1@gmail.com> > Cc: Murali Karicheri <m-karicheri2@ti.com> > Cc: Joao Pinto <Joao.Pinto@synopsys.com> > Cc: Stanimir Varbanov <svarbanov@mm-sol.com> > Cc: Pratyush Anand <pratyush.anand@gmail.com> > Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> > --- > drivers/pci/dwc/pci-dra7xx.c | 16 ++++++++-------- > drivers/pci/dwc/pci-exynos.c | 4 ++-- > drivers/pci/dwc/pci-keystone-dw.c | 4 ++-- > drivers/pci/dwc/pcie-designware.c | 12 ++++++------ > drivers/pci/dwc/pcie-designware.h | 4 ++-- > drivers/pci/dwc/pcie-qcom.c | 2 +- > drivers/pci/dwc/pcie-spear13xx.c | 24 ++++++++++++------------ > 7 files changed, 33 insertions(+), 33 deletions(-) > > diff --git a/drivers/pci/dwc/pci-dra7xx.c b/drivers/pci/dwc/pci-dra7xx.c > index aeeab74..38b0c9a 100644 > --- a/drivers/pci/dwc/pci-dra7xx.c > +++ b/drivers/pci/dwc/pci-dra7xx.c > @@ -114,22 +114,22 @@ static int dra7xx_pcie_establish_link(struct dra7xx_pcie *dra7xx) > } > > if (dra7xx->link_gen == 1) { > - dw_pcie_cfg_read(pp->dbi_base + exp_cap_off + PCI_EXP_LNKCAP, > - 4, ®); > + dw_pcie_read(pp->dbi_base + exp_cap_off + PCI_EXP_LNKCAP, > + 4, ®); > if ((reg & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) { > reg &= ~((u32)PCI_EXP_LNKCAP_SLS); > reg |= PCI_EXP_LNKCAP_SLS_2_5GB; > - dw_pcie_cfg_write(pp->dbi_base + exp_cap_off + > - PCI_EXP_LNKCAP, 4, reg); > + dw_pcie_write(pp->dbi_base + exp_cap_off + > + PCI_EXP_LNKCAP, 4, reg); > } > > - dw_pcie_cfg_read(pp->dbi_base + exp_cap_off + PCI_EXP_LNKCTL2, > - 2, ®); > + dw_pcie_read(pp->dbi_base + exp_cap_off + PCI_EXP_LNKCTL2, > + 2, ®); > if ((reg & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) { > reg &= ~((u32)PCI_EXP_LNKCAP_SLS); > reg |= PCI_EXP_LNKCAP_SLS_2_5GB; > - dw_pcie_cfg_write(pp->dbi_base + exp_cap_off + > - PCI_EXP_LNKCTL2, 2, reg); > + dw_pcie_write(pp->dbi_base + exp_cap_off + > + PCI_EXP_LNKCTL2, 2, reg); > } > } > > diff --git a/drivers/pci/dwc/pci-exynos.c b/drivers/pci/dwc/pci-exynos.c > index c179e7a..e3fbff4 100644 > --- a/drivers/pci/dwc/pci-exynos.c > +++ b/drivers/pci/dwc/pci-exynos.c > @@ -429,7 +429,7 @@ static int exynos_pcie_rd_own_conf(struct pcie_port *pp, int where, int size, > int ret; > > exynos_pcie_sideband_dbi_r_mode(exynos_pcie, true); > - ret = dw_pcie_cfg_read(pp->dbi_base + where, size, val); > + ret = dw_pcie_read(pp->dbi_base + where, size, val); > exynos_pcie_sideband_dbi_r_mode(exynos_pcie, false); > return ret; > } > @@ -441,7 +441,7 @@ static int exynos_pcie_wr_own_conf(struct pcie_port *pp, int where, int size, > int ret; > > exynos_pcie_sideband_dbi_w_mode(exynos_pcie, true); > - ret = dw_pcie_cfg_write(pp->dbi_base + where, size, val); > + ret = dw_pcie_write(pp->dbi_base + where, size, val); > exynos_pcie_sideband_dbi_w_mode(exynos_pcie, false); > return ret; > } > diff --git a/drivers/pci/dwc/pci-keystone-dw.c b/drivers/pci/dwc/pci-keystone-dw.c > index 9397c46..4875334 100644 > --- a/drivers/pci/dwc/pci-keystone-dw.c > +++ b/drivers/pci/dwc/pci-keystone-dw.c > @@ -444,7 +444,7 @@ int ks_dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus, > > addr = ks_pcie_cfg_setup(ks_pcie, bus_num, devfn); > > - return dw_pcie_cfg_read(addr + where, size, val); > + return dw_pcie_read(addr + where, size, val); > } > > int ks_dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus, > @@ -456,7 +456,7 @@ int ks_dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus, > > addr = ks_pcie_cfg_setup(ks_pcie, bus_num, devfn); > > - return dw_pcie_cfg_write(addr + where, size, val); > + return dw_pcie_write(addr + where, size, val); > } > > /** > diff --git a/drivers/pci/dwc/pcie-designware.c b/drivers/pci/dwc/pcie-designware.c > index 0b928dc..d0ea310 100644 > --- a/drivers/pci/dwc/pcie-designware.c > +++ b/drivers/pci/dwc/pcie-designware.c > @@ -33,7 +33,7 @@ > > static struct pci_ops dw_pcie_ops; > > -int dw_pcie_cfg_read(void __iomem *addr, int size, u32 *val) > +int dw_pcie_read(void __iomem *addr, int size, u32 *val) > { > if ((uintptr_t)addr & (size - 1)) { > *val = 0; > @@ -54,7 +54,7 @@ int dw_pcie_cfg_read(void __iomem *addr, int size, u32 *val) > return PCIBIOS_SUCCESSFUL; > } > > -int dw_pcie_cfg_write(void __iomem *addr, int size, u32 val) > +int dw_pcie_write(void __iomem *addr, int size, u32 val) > { > if ((uintptr_t)addr & (size - 1)) > return PCIBIOS_BAD_REGISTER_NUMBER; > @@ -108,7 +108,7 @@ static int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size, > if (pp->ops->rd_own_conf) > return pp->ops->rd_own_conf(pp, where, size, val); > > - return dw_pcie_cfg_read(pp->dbi_base + where, size, val); > + return dw_pcie_read(pp->dbi_base + where, size, val); > } > > static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size, > @@ -117,7 +117,7 @@ static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size, > if (pp->ops->wr_own_conf) > return pp->ops->wr_own_conf(pp, where, size, val); > > - return dw_pcie_cfg_write(pp->dbi_base + where, size, val); > + return dw_pcie_write(pp->dbi_base + where, size, val); > } > > static void dw_pcie_prog_outbound_atu(struct pcie_port *pp, int index, > @@ -638,7 +638,7 @@ static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus, > dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1, > type, cpu_addr, > busdev, cfg_size); > - ret = dw_pcie_cfg_read(va_cfg_base + where, size, val); > + ret = dw_pcie_read(va_cfg_base + where, size, val); > if (pp->num_viewport <= 2) > dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1, > PCIE_ATU_TYPE_IO, pp->io_base, > @@ -676,7 +676,7 @@ static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus, > dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1, > type, cpu_addr, > busdev, cfg_size); > - ret = dw_pcie_cfg_write(va_cfg_base + where, size, val); > + ret = dw_pcie_write(va_cfg_base + where, size, val); > if (pp->num_viewport <= 2) > dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1, > PCIE_ATU_TYPE_IO, pp->io_base, > diff --git a/drivers/pci/dwc/pcie-designware.h b/drivers/pci/dwc/pcie-designware.h > index a6cf9262..b6ddb05 100644 > --- a/drivers/pci/dwc/pcie-designware.h > +++ b/drivers/pci/dwc/pcie-designware.h > @@ -146,8 +146,8 @@ struct pcie_host_ops { > > u32 dw_pcie_readl_rc(struct pcie_port *pp, u32 reg); > void dw_pcie_writel_rc(struct pcie_port *pp, u32 reg, u32 val); > -int dw_pcie_cfg_read(void __iomem *addr, int size, u32 *val); > -int dw_pcie_cfg_write(void __iomem *addr, int size, u32 val); > +int dw_pcie_read(void __iomem *addr, int size, u32 *val); > +int dw_pcie_write(void __iomem *addr, int size, u32 val); > irqreturn_t dw_handle_msi_irq(struct pcie_port *pp); > void dw_pcie_msi_init(struct pcie_port *pp); > int dw_pcie_wait_for_link(struct pcie_port *pp); > diff --git a/drivers/pci/dwc/pcie-qcom.c b/drivers/pci/dwc/pcie-qcom.c > index 2c24c45..d75fc02 100644 > --- a/drivers/pci/dwc/pcie-qcom.c > +++ b/drivers/pci/dwc/pcie-qcom.c > @@ -630,7 +630,7 @@ static int qcom_pcie_rd_own_conf(struct pcie_port *pp, int where, int size, > return PCIBIOS_SUCCESSFUL; > } > > - return dw_pcie_cfg_read(pp->dbi_base + where, size, val); > + return dw_pcie_read(pp->dbi_base + where, size, val); > } > > static struct pcie_host_ops qcom_pcie_dw_ops = { > diff --git a/drivers/pci/dwc/pcie-spear13xx.c b/drivers/pci/dwc/pcie-spear13xx.c > index 5970566..7acf91e 100644 > --- a/drivers/pci/dwc/pcie-spear13xx.c > +++ b/drivers/pci/dwc/pcie-spear13xx.c > @@ -91,34 +91,34 @@ static int spear13xx_pcie_establish_link(struct spear13xx_pcie *spear13xx_pcie) > * default value in capability register is 512 bytes. So force > * it to 128 here. > */ > - dw_pcie_cfg_read(pp->dbi_base + exp_cap_off + PCI_EXP_DEVCTL, 2, &val); > + dw_pcie_read(pp->dbi_base + exp_cap_off + PCI_EXP_DEVCTL, 2, &val); > val &= ~PCI_EXP_DEVCTL_READRQ; > - dw_pcie_cfg_write(pp->dbi_base + exp_cap_off + PCI_EXP_DEVCTL, 2, val); > + dw_pcie_write(pp->dbi_base + exp_cap_off + PCI_EXP_DEVCTL, 2, val); > > - dw_pcie_cfg_write(pp->dbi_base + PCI_VENDOR_ID, 2, 0x104A); > - dw_pcie_cfg_write(pp->dbi_base + PCI_DEVICE_ID, 2, 0xCD80); > + dw_pcie_write(pp->dbi_base + PCI_VENDOR_ID, 2, 0x104A); > + dw_pcie_write(pp->dbi_base + PCI_DEVICE_ID, 2, 0xCD80); > > /* > * if is_gen1 is set then handle it, so that some buggy card > * also works > */ > if (spear13xx_pcie->is_gen1) { > - dw_pcie_cfg_read(pp->dbi_base + exp_cap_off + PCI_EXP_LNKCAP, > - 4, &val); > + dw_pcie_read(pp->dbi_base + exp_cap_off + PCI_EXP_LNKCAP, > + 4, &val); > if ((val & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) { > val &= ~((u32)PCI_EXP_LNKCAP_SLS); > val |= PCI_EXP_LNKCAP_SLS_2_5GB; > - dw_pcie_cfg_write(pp->dbi_base + exp_cap_off + > - PCI_EXP_LNKCAP, 4, val); > + dw_pcie_write(pp->dbi_base + exp_cap_off + > + PCI_EXP_LNKCAP, 4, val); > } > > - dw_pcie_cfg_read(pp->dbi_base + exp_cap_off + PCI_EXP_LNKCTL2, > - 2, &val); > + dw_pcie_read(pp->dbi_base + exp_cap_off + PCI_EXP_LNKCTL2, > + 2, &val); > if ((val & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) { > val &= ~((u32)PCI_EXP_LNKCAP_SLS); > val |= PCI_EXP_LNKCAP_SLS_2_5GB; > - dw_pcie_cfg_write(pp->dbi_base + exp_cap_off + > - PCI_EXP_LNKCTL2, 2, val); > + dw_pcie_write(pp->dbi_base + exp_cap_off + > + PCI_EXP_LNKCTL2, 2, val); > } > } > > Make sense. Reviewed-By: Joao Pinto <jpinto@synopsys.com> -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/drivers/pci/dwc/pci-dra7xx.c b/drivers/pci/dwc/pci-dra7xx.c index aeeab74..38b0c9a 100644 --- a/drivers/pci/dwc/pci-dra7xx.c +++ b/drivers/pci/dwc/pci-dra7xx.c @@ -114,22 +114,22 @@ static int dra7xx_pcie_establish_link(struct dra7xx_pcie *dra7xx) } if (dra7xx->link_gen == 1) { - dw_pcie_cfg_read(pp->dbi_base + exp_cap_off + PCI_EXP_LNKCAP, - 4, ®); + dw_pcie_read(pp->dbi_base + exp_cap_off + PCI_EXP_LNKCAP, + 4, ®); if ((reg & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) { reg &= ~((u32)PCI_EXP_LNKCAP_SLS); reg |= PCI_EXP_LNKCAP_SLS_2_5GB; - dw_pcie_cfg_write(pp->dbi_base + exp_cap_off + - PCI_EXP_LNKCAP, 4, reg); + dw_pcie_write(pp->dbi_base + exp_cap_off + + PCI_EXP_LNKCAP, 4, reg); } - dw_pcie_cfg_read(pp->dbi_base + exp_cap_off + PCI_EXP_LNKCTL2, - 2, ®); + dw_pcie_read(pp->dbi_base + exp_cap_off + PCI_EXP_LNKCTL2, + 2, ®); if ((reg & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) { reg &= ~((u32)PCI_EXP_LNKCAP_SLS); reg |= PCI_EXP_LNKCAP_SLS_2_5GB; - dw_pcie_cfg_write(pp->dbi_base + exp_cap_off + - PCI_EXP_LNKCTL2, 2, reg); + dw_pcie_write(pp->dbi_base + exp_cap_off + + PCI_EXP_LNKCTL2, 2, reg); } } diff --git a/drivers/pci/dwc/pci-exynos.c b/drivers/pci/dwc/pci-exynos.c index c179e7a..e3fbff4 100644 --- a/drivers/pci/dwc/pci-exynos.c +++ b/drivers/pci/dwc/pci-exynos.c @@ -429,7 +429,7 @@ static int exynos_pcie_rd_own_conf(struct pcie_port *pp, int where, int size, int ret; exynos_pcie_sideband_dbi_r_mode(exynos_pcie, true); - ret = dw_pcie_cfg_read(pp->dbi_base + where, size, val); + ret = dw_pcie_read(pp->dbi_base + where, size, val); exynos_pcie_sideband_dbi_r_mode(exynos_pcie, false); return ret; } @@ -441,7 +441,7 @@ static int exynos_pcie_wr_own_conf(struct pcie_port *pp, int where, int size, int ret; exynos_pcie_sideband_dbi_w_mode(exynos_pcie, true); - ret = dw_pcie_cfg_write(pp->dbi_base + where, size, val); + ret = dw_pcie_write(pp->dbi_base + where, size, val); exynos_pcie_sideband_dbi_w_mode(exynos_pcie, false); return ret; } diff --git a/drivers/pci/dwc/pci-keystone-dw.c b/drivers/pci/dwc/pci-keystone-dw.c index 9397c46..4875334 100644 --- a/drivers/pci/dwc/pci-keystone-dw.c +++ b/drivers/pci/dwc/pci-keystone-dw.c @@ -444,7 +444,7 @@ int ks_dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus, addr = ks_pcie_cfg_setup(ks_pcie, bus_num, devfn); - return dw_pcie_cfg_read(addr + where, size, val); + return dw_pcie_read(addr + where, size, val); } int ks_dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus, @@ -456,7 +456,7 @@ int ks_dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus, addr = ks_pcie_cfg_setup(ks_pcie, bus_num, devfn); - return dw_pcie_cfg_write(addr + where, size, val); + return dw_pcie_write(addr + where, size, val); } /** diff --git a/drivers/pci/dwc/pcie-designware.c b/drivers/pci/dwc/pcie-designware.c index 0b928dc..d0ea310 100644 --- a/drivers/pci/dwc/pcie-designware.c +++ b/drivers/pci/dwc/pcie-designware.c @@ -33,7 +33,7 @@ static struct pci_ops dw_pcie_ops; -int dw_pcie_cfg_read(void __iomem *addr, int size, u32 *val) +int dw_pcie_read(void __iomem *addr, int size, u32 *val) { if ((uintptr_t)addr & (size - 1)) { *val = 0; @@ -54,7 +54,7 @@ int dw_pcie_cfg_read(void __iomem *addr, int size, u32 *val) return PCIBIOS_SUCCESSFUL; } -int dw_pcie_cfg_write(void __iomem *addr, int size, u32 val) +int dw_pcie_write(void __iomem *addr, int size, u32 val) { if ((uintptr_t)addr & (size - 1)) return PCIBIOS_BAD_REGISTER_NUMBER; @@ -108,7 +108,7 @@ static int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size, if (pp->ops->rd_own_conf) return pp->ops->rd_own_conf(pp, where, size, val); - return dw_pcie_cfg_read(pp->dbi_base + where, size, val); + return dw_pcie_read(pp->dbi_base + where, size, val); } static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size, @@ -117,7 +117,7 @@ static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size, if (pp->ops->wr_own_conf) return pp->ops->wr_own_conf(pp, where, size, val); - return dw_pcie_cfg_write(pp->dbi_base + where, size, val); + return dw_pcie_write(pp->dbi_base + where, size, val); } static void dw_pcie_prog_outbound_atu(struct pcie_port *pp, int index, @@ -638,7 +638,7 @@ static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus, dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1, type, cpu_addr, busdev, cfg_size); - ret = dw_pcie_cfg_read(va_cfg_base + where, size, val); + ret = dw_pcie_read(va_cfg_base + where, size, val); if (pp->num_viewport <= 2) dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1, PCIE_ATU_TYPE_IO, pp->io_base, @@ -676,7 +676,7 @@ static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus, dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1, type, cpu_addr, busdev, cfg_size); - ret = dw_pcie_cfg_write(va_cfg_base + where, size, val); + ret = dw_pcie_write(va_cfg_base + where, size, val); if (pp->num_viewport <= 2) dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1, PCIE_ATU_TYPE_IO, pp->io_base, diff --git a/drivers/pci/dwc/pcie-designware.h b/drivers/pci/dwc/pcie-designware.h index a6cf9262..b6ddb05 100644 --- a/drivers/pci/dwc/pcie-designware.h +++ b/drivers/pci/dwc/pcie-designware.h @@ -146,8 +146,8 @@ struct pcie_host_ops { u32 dw_pcie_readl_rc(struct pcie_port *pp, u32 reg); void dw_pcie_writel_rc(struct pcie_port *pp, u32 reg, u32 val); -int dw_pcie_cfg_read(void __iomem *addr, int size, u32 *val); -int dw_pcie_cfg_write(void __iomem *addr, int size, u32 val); +int dw_pcie_read(void __iomem *addr, int size, u32 *val); +int dw_pcie_write(void __iomem *addr, int size, u32 val); irqreturn_t dw_handle_msi_irq(struct pcie_port *pp); void dw_pcie_msi_init(struct pcie_port *pp); int dw_pcie_wait_for_link(struct pcie_port *pp); diff --git a/drivers/pci/dwc/pcie-qcom.c b/drivers/pci/dwc/pcie-qcom.c index 2c24c45..d75fc02 100644 --- a/drivers/pci/dwc/pcie-qcom.c +++ b/drivers/pci/dwc/pcie-qcom.c @@ -630,7 +630,7 @@ static int qcom_pcie_rd_own_conf(struct pcie_port *pp, int where, int size, return PCIBIOS_SUCCESSFUL; } - return dw_pcie_cfg_read(pp->dbi_base + where, size, val); + return dw_pcie_read(pp->dbi_base + where, size, val); } static struct pcie_host_ops qcom_pcie_dw_ops = { diff --git a/drivers/pci/dwc/pcie-spear13xx.c b/drivers/pci/dwc/pcie-spear13xx.c index 5970566..7acf91e 100644 --- a/drivers/pci/dwc/pcie-spear13xx.c +++ b/drivers/pci/dwc/pcie-spear13xx.c @@ -91,34 +91,34 @@ static int spear13xx_pcie_establish_link(struct spear13xx_pcie *spear13xx_pcie) * default value in capability register is 512 bytes. So force * it to 128 here. */ - dw_pcie_cfg_read(pp->dbi_base + exp_cap_off + PCI_EXP_DEVCTL, 2, &val); + dw_pcie_read(pp->dbi_base + exp_cap_off + PCI_EXP_DEVCTL, 2, &val); val &= ~PCI_EXP_DEVCTL_READRQ; - dw_pcie_cfg_write(pp->dbi_base + exp_cap_off + PCI_EXP_DEVCTL, 2, val); + dw_pcie_write(pp->dbi_base + exp_cap_off + PCI_EXP_DEVCTL, 2, val); - dw_pcie_cfg_write(pp->dbi_base + PCI_VENDOR_ID, 2, 0x104A); - dw_pcie_cfg_write(pp->dbi_base + PCI_DEVICE_ID, 2, 0xCD80); + dw_pcie_write(pp->dbi_base + PCI_VENDOR_ID, 2, 0x104A); + dw_pcie_write(pp->dbi_base + PCI_DEVICE_ID, 2, 0xCD80); /* * if is_gen1 is set then handle it, so that some buggy card * also works */ if (spear13xx_pcie->is_gen1) { - dw_pcie_cfg_read(pp->dbi_base + exp_cap_off + PCI_EXP_LNKCAP, - 4, &val); + dw_pcie_read(pp->dbi_base + exp_cap_off + PCI_EXP_LNKCAP, + 4, &val); if ((val & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) { val &= ~((u32)PCI_EXP_LNKCAP_SLS); val |= PCI_EXP_LNKCAP_SLS_2_5GB; - dw_pcie_cfg_write(pp->dbi_base + exp_cap_off + - PCI_EXP_LNKCAP, 4, val); + dw_pcie_write(pp->dbi_base + exp_cap_off + + PCI_EXP_LNKCAP, 4, val); } - dw_pcie_cfg_read(pp->dbi_base + exp_cap_off + PCI_EXP_LNKCTL2, - 2, &val); + dw_pcie_read(pp->dbi_base + exp_cap_off + PCI_EXP_LNKCTL2, + 2, &val); if ((val & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) { val &= ~((u32)PCI_EXP_LNKCAP_SLS); val |= PCI_EXP_LNKCAP_SLS_2_5GB; - dw_pcie_cfg_write(pp->dbi_base + exp_cap_off + - PCI_EXP_LNKCTL2, 2, val); + dw_pcie_write(pp->dbi_base + exp_cap_off + + PCI_EXP_LNKCTL2, 2, val); } }
No functional change. dw_pcie_cfg_read/dw_pcie_cfg_write doesn't do anything specific to access configuration space. It can be just renamed to dw_pcie_read/dw_pcie_write and used to read/write data to dbi space. This is in preparation for added endpoint support to linux kernel. Cc: Jingoo Han <jingoohan1@gmail.com> Cc: Murali Karicheri <m-karicheri2@ti.com> Cc: Joao Pinto <Joao.Pinto@synopsys.com> Cc: Stanimir Varbanov <svarbanov@mm-sol.com> Cc: Pratyush Anand <pratyush.anand@gmail.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> --- drivers/pci/dwc/pci-dra7xx.c | 16 ++++++++-------- drivers/pci/dwc/pci-exynos.c | 4 ++-- drivers/pci/dwc/pci-keystone-dw.c | 4 ++-- drivers/pci/dwc/pcie-designware.c | 12 ++++++------ drivers/pci/dwc/pcie-designware.h | 4 ++-- drivers/pci/dwc/pcie-qcom.c | 2 +- drivers/pci/dwc/pcie-spear13xx.c | 24 ++++++++++++------------ 7 files changed, 33 insertions(+), 33 deletions(-)