| Message ID | 1484727218-3499-1-git-send-email-leo.yan@linaro.org (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
On 01/18, Leo Yan wrote: > In clock driver initialize phase the spinlock is missed to assignment > to struct clkgate_separated, finally there have no locking to protect > exclusive accessing for clock registers. > > This bug introduces the console has no output after enable coresight > driver on 96borads Hikey; this is because console using UART3, which s/borads/boards/ > has shared the same register with coresight clock enabling bit. After > applied this patch it can assign lock properly to protect exclusive > accessing, and console can work well after enabled coresight modules. > > Signed-off-by: Leo Yan <leo.yan@linaro.org> Is there a Fixes: tag needed? Is coresight support merged into Linus' tree? I want to know if this needs to be applied for v4.10 or can wait until v4.11.
On Fri, Jan 20, 2017 at 02:58:27PM -0800, Stephen Boyd wrote: > On 01/18, Leo Yan wrote: > > In clock driver initialize phase the spinlock is missed to assignment > > to struct clkgate_separated, finally there have no locking to protect > > exclusive accessing for clock registers. > > > > This bug introduces the console has no output after enable coresight > > driver on 96borads Hikey; this is because console using UART3, which > > s/borads/boards/ > > > has shared the same register with coresight clock enabling bit. After > > applied this patch it can assign lock properly to protect exclusive > > accessing, and console can work well after enabled coresight modules. > > > > Signed-off-by: Leo Yan <leo.yan@linaro.org> > > Is there a Fixes: tag needed? Thanks for reviewing, will send new patch for upper comments. > Is coresight support merged into Linus' tree? I want to know if > this needs to be applied for v4.10 or can wait until v4.11. No, Coresight patch has not been merged. Should meantion one thing is: this issue impacts all gate clocks if they share same register, there have many such kind clocks for Hi6220. So it's not only for coresight and uart clocks. Thanks, Leo Yan -- To unsubscribe from this list: send the line "unsubscribe linux-clk" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/drivers/clk/hisilicon/clkgate-separated.c b/drivers/clk/hisilicon/clkgate-separated.c index a47812f..7908bc3 100644 --- a/drivers/clk/hisilicon/clkgate-separated.c +++ b/drivers/clk/hisilicon/clkgate-separated.c @@ -120,6 +120,7 @@ struct clk *hisi_register_clkgate_sep(struct device *dev, const char *name, sclk->bit_idx = bit_idx; sclk->flags = clk_gate_flags; sclk->hw.init = &init; + sclk->lock = lock; clk = clk_register(dev, &sclk->hw); if (IS_ERR(clk))
In clock driver initialize phase the spinlock is missed to assignment to struct clkgate_separated, finally there have no locking to protect exclusive accessing for clock registers. This bug introduces the console has no output after enable coresight driver on 96borads Hikey; this is because console using UART3, which has shared the same register with coresight clock enabling bit. After applied this patch it can assign lock properly to protect exclusive accessing, and console can work well after enabled coresight modules. Signed-off-by: Leo Yan <leo.yan@linaro.org> --- drivers/clk/hisilicon/clkgate-separated.c | 1 + 1 file changed, 1 insertion(+)