| Message ID | 1487585521-19445-2-git-send-email-nikunj@linux.vnet.ibm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 02/20/2017 09:11 PM, Nikunj A Dadhania wrote: > +#ifndef TARGET_PPC64 > static inline target_ulong cpu_read_xer(CPUPPCState *env) > { > return env->xer | (env->so << XER_SO) | (env->ov << XER_OV) | (env->ca << XER_CA); > } > +#else > +static inline target_ulong cpu_read_xer(CPUPPCState *env) > +{ > + return env->xer | (env->so << XER_SO) | > + (env->ov << XER_OV) | (env->ca << XER_CA) | > + (env->ov32 << XER_OV32) | (env->ca32 << XER_CA32); > +} > +#endif > > +#ifndef TARGET_PPC64 > static inline void cpu_write_xer(CPUPPCState *env, target_ulong xer) > { > env->so = (xer >> XER_SO) & 1; > @@ -2355,6 +2371,20 @@ static inline void cpu_write_xer(CPUPPCState *env, target_ulong xer) > env->ca = (xer >> XER_CA) & 1; > env->xer = xer & ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA)); > } > +#else > +static inline void cpu_write_xer(CPUPPCState *env, target_ulong xer) > +{ > + env->so = (xer >> XER_SO) & 1; > + env->ov = (xer >> XER_OV) & 1; > + env->ca = (xer >> XER_CA) & 1; > + env->ov32 = (xer >> XER_OV32) & 1; > + env->ca32 = (xer >> XER_CA32) & 1; > + env->xer = xer & ~((1ul << XER_SO) | > + (1ul << XER_OV) | (1ul << XER_CA) | > + (1ul << XER_OV32) | (1ul << XER_CA32)); > +} > +#endif You should probably move both of these out of line now (perhaps cpu.c). You probably don't want to set ov32/ca32 unless the cpu is power9. I assume that if you attempt to set these bits for power8 they are read-as-zero/write-ignore? > @@ -3715,6 +3719,12 @@ static void gen_read_xer(TCGv dst) > tcg_gen_or_tl(t0, t0, t1); > tcg_gen_or_tl(dst, dst, t2); > tcg_gen_or_tl(dst, dst, t0); > +#ifdef TARGET_PPC64 > + tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32); > + tcg_gen_or_tl(dst, dst, t0); > + tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32); > + tcg_gen_or_tl(dst, dst, t0); > +#endif > tcg_temp_free(t0); > tcg_temp_free(t1); > tcg_temp_free(t2); > @@ -3727,9 +3737,14 @@ static void gen_write_xer(TCGv src) > tcg_gen_shri_tl(cpu_so, src, XER_SO); > tcg_gen_shri_tl(cpu_ov, src, XER_OV); > tcg_gen_shri_tl(cpu_ca, src, XER_CA); > + tcg_gen_shri_tl(cpu_ov32, src, XER_OV32); > + tcg_gen_shri_tl(cpu_ca32, src, XER_CA32); > tcg_gen_andi_tl(cpu_so, cpu_so, 1); > tcg_gen_andi_tl(cpu_ov, cpu_ov, 1); > tcg_gen_andi_tl(cpu_ca, cpu_ca, 1); > + tcg_gen_andi_tl(cpu_ov32, cpu_ov32, 1); > + tcg_gen_andi_tl(cpu_ca32, cpu_ca32, 1); > + > } Watch the blank lines. No ifdef here on the write side? r~
Richard Henderson <rth@twiddle.net> writes: > On 02/20/2017 09:11 PM, Nikunj A Dadhania wrote: >> +#ifndef TARGET_PPC64 >> static inline target_ulong cpu_read_xer(CPUPPCState *env) >> { >> return env->xer | (env->so << XER_SO) | (env->ov << XER_OV) | (env->ca << XER_CA); >> } >> +#else >> +static inline target_ulong cpu_read_xer(CPUPPCState *env) >> +{ >> + return env->xer | (env->so << XER_SO) | >> + (env->ov << XER_OV) | (env->ca << XER_CA) | >> + (env->ov32 << XER_OV32) | (env->ca32 << XER_CA32); >> +} >> +#endif >> >> +#ifndef TARGET_PPC64 >> static inline void cpu_write_xer(CPUPPCState *env, target_ulong xer) >> { >> env->so = (xer >> XER_SO) & 1; >> @@ -2355,6 +2371,20 @@ static inline void cpu_write_xer(CPUPPCState *env, target_ulong xer) >> env->ca = (xer >> XER_CA) & 1; >> env->xer = xer & ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA)); >> } >> +#else >> +static inline void cpu_write_xer(CPUPPCState *env, target_ulong xer) >> +{ >> + env->so = (xer >> XER_SO) & 1; >> + env->ov = (xer >> XER_OV) & 1; >> + env->ca = (xer >> XER_CA) & 1; >> + env->ov32 = (xer >> XER_OV32) & 1; >> + env->ca32 = (xer >> XER_CA32) & 1; >> + env->xer = xer & ~((1ul << XER_SO) | >> + (1ul << XER_OV) | (1ul << XER_CA) | >> + (1ul << XER_OV32) | (1ul << XER_CA32)); >> +} >> +#endif > > You should probably move both of these out of line now (perhaps cpu.c). Sure. > You probably don't want to set ov32/ca32 unless the cpu is power9. I assume > that if you attempt to set these bits for power8 they are > read-as-zero/write-ignore? Sure, will make it CPU specific. >> @@ -3715,6 +3719,12 @@ static void gen_read_xer(TCGv dst) >> tcg_gen_or_tl(t0, t0, t1); >> tcg_gen_or_tl(dst, dst, t2); >> tcg_gen_or_tl(dst, dst, t0); >> +#ifdef TARGET_PPC64 >> + tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32); >> + tcg_gen_or_tl(dst, dst, t0); >> + tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32); >> + tcg_gen_or_tl(dst, dst, t0); >> +#endif >> tcg_temp_free(t0); >> tcg_temp_free(t1); >> tcg_temp_free(t2); >> @@ -3727,9 +3737,14 @@ static void gen_write_xer(TCGv src) >> tcg_gen_shri_tl(cpu_so, src, XER_SO); >> tcg_gen_shri_tl(cpu_ov, src, XER_OV); >> tcg_gen_shri_tl(cpu_ca, src, XER_CA); >> + tcg_gen_shri_tl(cpu_ov32, src, XER_OV32); >> + tcg_gen_shri_tl(cpu_ca32, src, XER_CA32); >> tcg_gen_andi_tl(cpu_so, cpu_so, 1); >> tcg_gen_andi_tl(cpu_ov, cpu_ov, 1); >> tcg_gen_andi_tl(cpu_ca, cpu_ca, 1); >> + tcg_gen_andi_tl(cpu_ov32, cpu_ov32, 1); >> + tcg_gen_andi_tl(cpu_ca32, cpu_ca32, 1); >> + >> } > > Watch the blank lines. No ifdef here on the write side? Right, will add. Regards Nikunj
On Tue, Feb 21, 2017 at 10:15:46AM +0530, Nikunj A Dadhania wrote: > Richard Henderson <rth@twiddle.net> writes: > > > On 02/20/2017 09:11 PM, Nikunj A Dadhania wrote: > >> +#ifndef TARGET_PPC64 > >> static inline target_ulong cpu_read_xer(CPUPPCState *env) > >> { > >> return env->xer | (env->so << XER_SO) | (env->ov << XER_OV) | (env->ca << XER_CA); > >> } > >> +#else > >> +static inline target_ulong cpu_read_xer(CPUPPCState *env) > >> +{ > >> + return env->xer | (env->so << XER_SO) | > >> + (env->ov << XER_OV) | (env->ca << XER_CA) | > >> + (env->ov32 << XER_OV32) | (env->ca32 << XER_CA32); > >> +} > >> +#endif > >> > >> +#ifndef TARGET_PPC64 > >> static inline void cpu_write_xer(CPUPPCState *env, target_ulong xer) > >> { > >> env->so = (xer >> XER_SO) & 1; > >> @@ -2355,6 +2371,20 @@ static inline void cpu_write_xer(CPUPPCState *env, target_ulong xer) > >> env->ca = (xer >> XER_CA) & 1; > >> env->xer = xer & ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA)); > >> } > >> +#else > >> +static inline void cpu_write_xer(CPUPPCState *env, target_ulong xer) > >> +{ > >> + env->so = (xer >> XER_SO) & 1; > >> + env->ov = (xer >> XER_OV) & 1; > >> + env->ca = (xer >> XER_CA) & 1; > >> + env->ov32 = (xer >> XER_OV32) & 1; > >> + env->ca32 = (xer >> XER_CA32) & 1; > >> + env->xer = xer & ~((1ul << XER_SO) | > >> + (1ul << XER_OV) | (1ul << XER_CA) | > >> + (1ul << XER_OV32) | (1ul << XER_CA32)); > >> +} > >> +#endif > > > > You should probably move both of these out of line now (perhaps cpu.c). > > Sure. > > > > You probably don't want to set ov32/ca32 unless the cpu is power9. I assume > > that if you attempt to set these bits for power8 they are > > read-as-zero/write-ignore? > > Sure, will make it CPU specific. Right, and given you need a CPU model check anyway, I don't see that there's any benefit to splitting out the 32-bit build version versus the 64-bit build version. > >> @@ -3715,6 +3719,12 @@ static void gen_read_xer(TCGv dst) > >> tcg_gen_or_tl(t0, t0, t1); > >> tcg_gen_or_tl(dst, dst, t2); > >> tcg_gen_or_tl(dst, dst, t0); > >> +#ifdef TARGET_PPC64 > >> + tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32); > >> + tcg_gen_or_tl(dst, dst, t0); > >> + tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32); > >> + tcg_gen_or_tl(dst, dst, t0); > >> +#endif > >> tcg_temp_free(t0); > >> tcg_temp_free(t1); > >> tcg_temp_free(t2); > >> @@ -3727,9 +3737,14 @@ static void gen_write_xer(TCGv src) > >> tcg_gen_shri_tl(cpu_so, src, XER_SO); > >> tcg_gen_shri_tl(cpu_ov, src, XER_OV); > >> tcg_gen_shri_tl(cpu_ca, src, XER_CA); > >> + tcg_gen_shri_tl(cpu_ov32, src, XER_OV32); > >> + tcg_gen_shri_tl(cpu_ca32, src, XER_CA32); > >> tcg_gen_andi_tl(cpu_so, cpu_so, 1); > >> tcg_gen_andi_tl(cpu_ov, cpu_ov, 1); > >> tcg_gen_andi_tl(cpu_ca, cpu_ca, 1); > >> + tcg_gen_andi_tl(cpu_ov32, cpu_ov32, 1); > >> + tcg_gen_andi_tl(cpu_ca32, cpu_ca32, 1); > >> + > >> } > > > > Watch the blank lines. No ifdef here on the write side? > > Right, will add. > > Regards > Nikunj >
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 425e79d..ef392f0 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -965,6 +965,8 @@ struct CPUPPCState { target_ulong so; target_ulong ov; target_ulong ca; + target_ulong ov32; + target_ulong ca32; /* Reservation address */ target_ulong reserve_addr; /* Reservation value */ @@ -1372,11 +1374,15 @@ int ppc_compat_max_threads(PowerPCCPU *cpu); #define XER_SO 31 #define XER_OV 30 #define XER_CA 29 +#define XER_OV32 19 +#define XER_CA32 18 #define XER_CMP 8 #define XER_BC 0 #define xer_so (env->so) #define xer_ov (env->ov) #define xer_ca (env->ca) +#define xer_ov32 (env->ov) +#define xer_ca32 (env->ca) #define xer_cmp ((env->xer >> XER_CMP) & 0xFF) #define xer_bc ((env->xer >> XER_BC) & 0x7F) @@ -2343,11 +2349,21 @@ enum { /*****************************************************************************/ +#ifndef TARGET_PPC64 static inline target_ulong cpu_read_xer(CPUPPCState *env) { return env->xer | (env->so << XER_SO) | (env->ov << XER_OV) | (env->ca << XER_CA); } +#else +static inline target_ulong cpu_read_xer(CPUPPCState *env) +{ + return env->xer | (env->so << XER_SO) | + (env->ov << XER_OV) | (env->ca << XER_CA) | + (env->ov32 << XER_OV32) | (env->ca32 << XER_CA32); +} +#endif +#ifndef TARGET_PPC64 static inline void cpu_write_xer(CPUPPCState *env, target_ulong xer) { env->so = (xer >> XER_SO) & 1; @@ -2355,6 +2371,20 @@ static inline void cpu_write_xer(CPUPPCState *env, target_ulong xer) env->ca = (xer >> XER_CA) & 1; env->xer = xer & ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA)); } +#else +static inline void cpu_write_xer(CPUPPCState *env, target_ulong xer) +{ + env->so = (xer >> XER_SO) & 1; + env->ov = (xer >> XER_OV) & 1; + env->ca = (xer >> XER_CA) & 1; + env->ov32 = (xer >> XER_OV32) & 1; + env->ca32 = (xer >> XER_CA32) & 1; + env->xer = xer & ~((1ul << XER_SO) | + (1ul << XER_OV) | (1ul << XER_CA) | + (1ul << XER_OV32) | (1ul << XER_CA32)); +} +#endif + static inline void cpu_get_tb_cpu_state(CPUPPCState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *flags) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 3ba2616..498b095 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -71,7 +71,7 @@ static TCGv cpu_lr; #if defined(TARGET_PPC64) static TCGv cpu_cfar; #endif -static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca; +static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32; static TCGv cpu_reserve; static TCGv cpu_fpscr; static TCGv_i32 cpu_access_type; @@ -173,6 +173,10 @@ void ppc_translate_init(void) offsetof(CPUPPCState, ov), "OV"); cpu_ca = tcg_global_mem_new(cpu_env, offsetof(CPUPPCState, ca), "CA"); + cpu_ov32 = tcg_global_mem_new(cpu_env, + offsetof(CPUPPCState, ov32), "OV32"); + cpu_ca32 = tcg_global_mem_new(cpu_env, + offsetof(CPUPPCState, ca32), "CA32"); cpu_reserve = tcg_global_mem_new(cpu_env, offsetof(CPUPPCState, reserve_addr), @@ -3715,6 +3719,12 @@ static void gen_read_xer(TCGv dst) tcg_gen_or_tl(t0, t0, t1); tcg_gen_or_tl(dst, dst, t2); tcg_gen_or_tl(dst, dst, t0); +#ifdef TARGET_PPC64 + tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32); + tcg_gen_or_tl(dst, dst, t0); + tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32); + tcg_gen_or_tl(dst, dst, t0); +#endif tcg_temp_free(t0); tcg_temp_free(t1); tcg_temp_free(t2); @@ -3727,9 +3737,14 @@ static void gen_write_xer(TCGv src) tcg_gen_shri_tl(cpu_so, src, XER_SO); tcg_gen_shri_tl(cpu_ov, src, XER_OV); tcg_gen_shri_tl(cpu_ca, src, XER_CA); + tcg_gen_shri_tl(cpu_ov32, src, XER_OV32); + tcg_gen_shri_tl(cpu_ca32, src, XER_CA32); tcg_gen_andi_tl(cpu_so, cpu_so, 1); tcg_gen_andi_tl(cpu_ov, cpu_ov, 1); tcg_gen_andi_tl(cpu_ca, cpu_ca, 1); + tcg_gen_andi_tl(cpu_ov32, cpu_ov32, 1); + tcg_gen_andi_tl(cpu_ca32, cpu_ca32, 1); + } /* mcrxr */
POWER ISA 3.0 adds CA32 and OV32 status in 64-bit mode. Add the flags and corresponding defines. Moreover, CA32 is updated when CA is updated and OV32 is updated when OV is updated. Arithmetic instructions: * Addition and Substractions: addic, addic., subfic, addc, subfc, adde, subfe, addme, subfme, addze, and subfze always updates CA and CA32. => CA reflects the carry out of bit 0 in 64-bit mode and out of bit 32 in 32-bit mode. => CA32 reflects the carry out of bit 32 independent of the mode. => SO and OV reflects overflow of the 64-bit result in 64-bit mode and overflow of the low-order 32-bit result in 32-bit mode => OV32 reflects overflow of the low-order 32-bit independent of the mode * Multiply Low and Divide: For mulld, divd, divde, divdu and divdeu: SO, OV, and OV32 bits reflects overflow of the 64-bit result For mullw, divw, divwe, divwu and divweu: SO, OV, and OV32 bits reflects overflow of the 32-bit result * Negate with OE=1 (nego) For 64-bit mode if the register RA contains 0x8000_0000_0000_0000, OV and OV32 are set to 1. For 32-bit mode if the register RA contains 0x8000_0000, OV and OV32 are set to 1. Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> --- target/ppc/cpu.h | 30 ++++++++++++++++++++++++++++++ target/ppc/translate.c | 17 ++++++++++++++++- 2 files changed, 46 insertions(+), 1 deletion(-)