| Message ID | 1482316017-22154-2-git-send-email-thomas.petazzoni@free-electrons.com (mailing list archive) |
|---|---|
| State | Accepted, archived |
| Delegated to: | Stephen Boyd |
| Headers | show |
On 12/21, Thomas Petazzoni wrote: > It turns out that in the CP110 HW block present in Marvell Armada > 7K/8K SoCs, gatable clock n°18 not only controls SD/MMC, but also the > GOP block. This commit updates the Device Tree binding for this piece > of hardware accordingly. > > Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> > --- Applied to clk-next
Stephen, On Wed, 21 Dec 2016 16:14:53 -0800, Stephen Boyd wrote: > On 12/21, Thomas Petazzoni wrote: > > It turns out that in the CP110 HW block present in Marvell Armada > > 7K/8K SoCs, gatable clock n°18 not only controls SD/MMC, but also the > > GOP block. This commit updates the Device Tree binding for this piece > > of hardware accordingly. > > > > Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> > > --- > > Applied to clk-next Even though you said you applied it, I still don't see this patch in mainline, while PATCH 2/3 of this series is now in mainline. Was this patch forgotten? Let me know if I should resend it, but I'm pretty sure it still applies, since no other changes on this file have been merged since quite a while. Thanks, Thomas
On 03/01, Thomas Petazzoni wrote: > Stephen, > > On Wed, 21 Dec 2016 16:14:53 -0800, Stephen Boyd wrote: > > On 12/21, Thomas Petazzoni wrote: > > > It turns out that in the CP110 HW block present in Marvell Armada > > > 7K/8K SoCs, gatable clock n°18 not only controls SD/MMC, but also the > > > GOP block. This commit updates the Device Tree binding for this piece > > > of hardware accordingly. > > > > > > Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> > > > --- > > > > Applied to clk-next > > Even though you said you applied it, I still don't see this patch in > mainline, while PATCH 2/3 of this series is now in mainline. > > Was this patch forgotten? Let me know if I should resend it, but I'm > pretty sure it still applies, since no other changes on this file have > been merged since quite a while. > No worries. I've made a note to put it into the fixes queue to send off after rc1.
Hello, On Wed, 1 Mar 2017 11:01:27 -0800, Stephen Boyd wrote: > > Even though you said you applied it, I still don't see this patch in > > mainline, while PATCH 2/3 of this series is now in mainline. > > > > Was this patch forgotten? Let me know if I should resend it, but I'm > > pretty sure it still applies, since no other changes on this file have > > been merged since quite a while. > > > > No worries. I've made a note to put it into the fixes queue to > send off after rc1. Great, thanks a lot. It's not a big thing, but it keeps popping up in my list of "things accepted by the maintainer, but not yet completely merged upstream" :-) Thomas
diff --git a/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt b/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt index 30c5469..07dbb35 100644 --- a/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt +++ b/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt @@ -45,7 +45,7 @@ The following clocks are available: - 1 15 SATA - 1 16 SATA USB - 1 17 Main - - 1 18 SD/MMC + - 1 18 SD/MMC/GOP - 1 21 Slow IO (SPI, NOR, BootROM, I2C, UART) - 1 22 USB3H0 - 1 23 USB3H1 @@ -65,7 +65,7 @@ Required properties: "cpm-audio", "cpm-communit", "cpm-nand", "cpm-ppv2", "cpm-sdio", "cpm-mg-domain", "cpm-mg-core", "cpm-xor1", "cpm-xor0", "cpm-gop-dp", "none", "cpm-pcie_x10", "cpm-pcie_x11", "cpm-pcie_x4", "cpm-pcie-xor", "cpm-sata", - "cpm-sata-usb", "cpm-main", "cpm-sd-mmc", "none", "none", "cpm-slow-io", + "cpm-sata-usb", "cpm-main", "cpm-sd-mmc-gop", "none", "none", "cpm-slow-io", "cpm-usb3h0", "cpm-usb3h1", "cpm-usb3dev", "cpm-eip150", "cpm-eip197"; Example: @@ -78,6 +78,6 @@ Example: gate-clock-output-names = "cpm-audio", "cpm-communit", "cpm-nand", "cpm-ppv2", "cpm-sdio", "cpm-mg-domain", "cpm-mg-core", "cpm-xor1", "cpm-xor0", "cpm-gop-dp", "none", "cpm-pcie_x10", "cpm-pcie_x11", "cpm-pcie_x4", "cpm-pcie-xor", "cpm-sata", - "cpm-sata-usb", "cpm-main", "cpm-sd-mmc", "none", "none", "cpm-slow-io", + "cpm-sata-usb", "cpm-main", "cpm-sd-mmc-gop", "none", "none", "cpm-slow-io", "cpm-usb3h0", "cpm-usb3h1", "cpm-usb3dev", "cpm-eip150", "cpm-eip197"; };
It turns out that in the CP110 HW block present in Marvell Armada 7K/8K SoCs, gatable clock n°18 not only controls SD/MMC, but also the GOP block. This commit updates the Device Tree binding for this piece of hardware accordingly. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> --- .../devicetree/bindings/arm/marvell/cp110-system-controller0.txt | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)