| Message ID | 20170306223449.21404-2-icenowy@aosc.xyz (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Tue, Mar 7, 2017 at 6:34 AM, Icenowy Zheng <icenowy@aosc.xyz> wrote: > Allwinner H3/V3s/A64 SoCs have a special USB PHY0 that can route to two > controllers: one is MUSB and the other is a EHCI/OHCI pair. > > When it's routed to EHCI/OHCI pair, it will needs a "pmu0" regs to > tweak, like other EHCI/OHCI pairs in Allwinner SoCs. > > Add this to the binding of USB PHYs on Allwinner H3/V3s/A64. > > Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Acked-by: Chen-Yu Tsai <wens@csie.org>
diff --git a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt index e42334258185..005bc22938ff 100644 --- a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt +++ b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt @@ -15,6 +15,7 @@ Required properties: - reg : a list of offset + length pairs - reg-names : * "phy_ctrl" + * "pmu0" for H3, V3s and A64 * "pmu1" * "pmu2" for sun4i, sun6i or sun7i - #phy-cells : from the generic phy bindings, must be 1
Allwinner H3/V3s/A64 SoCs have a special USB PHY0 that can route to two controllers: one is MUSB and the other is a EHCI/OHCI pair. When it's routed to EHCI/OHCI pair, it will needs a "pmu0" regs to tweak, like other EHCI/OHCI pairs in Allwinner SoCs. Add this to the binding of USB PHYs on Allwinner H3/V3s/A64. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> --- New patch in v3. Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt | 1 + 1 file changed, 1 insertion(+)