diff mbox

clk: renesas: r8a7796: Add HDMI clocks

Message ID 20170621090150.3868-1-laurent.pinchart+renesas@ideasonboard.com (mailing list archive)
State Superseded
Headers show

Commit Message

Laurent Pinchart June 21, 2017, 9:01 a.m. UTC
Add the HDMI and HDMI0 clocks to the R8A7796 CPG/MSSR driver.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
 drivers/clk/renesas/r8a7796-cpg-mssr.c | 2 ++
 1 file changed, 2 insertions(+)

Hi Geert,

I'd like to upstream HDMI output support on M3-W in v4.14. To ease dependency
handling, it would be great if this patch could already make it to v4.13.

Comments

Geert Uytterhoeven June 21, 2017, 9:16 a.m. UTC | #1
Hi Laurent,

On Wed, Jun 21, 2017 at 11:01 AM, Laurent Pinchart
<laurent.pinchart+renesas@ideasonboard.com> wrote:
> Add the HDMI and HDMI0 clocks to the R8A7796 CPG/MSSR driver.
>
> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> ---
>  drivers/clk/renesas/r8a7796-cpg-mssr.c | 2 ++
>  1 file changed, 2 insertions(+)
>
> Hi Geert,
>
> I'd like to upstream HDMI output support on M3-W in v4.14. To ease dependency
> handling, it would be great if this patch could already make it to v4.13.

I believe a similar patch is already in clk-next, destined for v4.13?

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds
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diff mbox

Patch

diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c
index 9d114b31b073..1d8c5c2b6174 100644
--- a/drivers/clk/renesas/r8a7796-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c
@@ -106,6 +106,7 @@  static const struct cpg_core_clk r8a7796_core_clks[] __initconst = {
 	DEF_DIV6P1("canfd",     R8A7796_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
 	DEF_DIV6P1("csi0",      R8A7796_CLK_CSI0,  CLK_PLL1_DIV4, 0x00c),
 	DEF_DIV6P1("mso",       R8A7796_CLK_MSO,   CLK_PLL1_DIV4, 0x014),
+	DEF_DIV6P1("hdmi",      R8A7796_CLK_HDMI,  CLK_PLL1_DIV4, 0x250),
 
 	DEF_DIV6_RO("osc",      R8A7796_CLK_OSC,   CLK_EXTAL, CPG_RCKCR,  8),
 	DEF_DIV6_RO("r_int",    CLK_RINT,          CLK_EXTAL, CPG_RCKCR, 32),
@@ -170,6 +171,7 @@  static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = {
 	DEF_MOD("du1",			 723,	R8A7796_CLK_S2D1),
 	DEF_MOD("du0",			 724,	R8A7796_CLK_S2D1),
 	DEF_MOD("lvds",			 727,	R8A7796_CLK_S2D1),
+	DEF_MOD("hdmi0",		 729,	R8A7796_CLK_HDMI),
 	DEF_MOD("vin7",			 804,	R8A7796_CLK_S0D2),
 	DEF_MOD("vin6",			 805,	R8A7796_CLK_S0D2),
 	DEF_MOD("vin5",			 806,	R8A7796_CLK_S0D2),