@@ -63,6 +63,7 @@
enum psr_feat_type {
FEAT_TYPE_L3_CAT,
FEAT_TYPE_L3_CDP,
+ FEAT_TYPE_L2_CAT,
FEAT_TYPE_NUM,
FEAT_TYPE_UNKNOWN,
};
@@ -160,6 +161,7 @@ static DEFINE_PER_CPU(struct psr_assoc, psr_assoc);
*/
static struct feat_node *feat_l3_cat;
static struct feat_node *feat_l3_cdp;
+static struct feat_node *feat_l2_cat;
/* Common functions */
#define cat_default_val(len) (0xffffffff >> (32 - (len)))
@@ -269,6 +271,12 @@ static bool psr_check_cbm(unsigned int cbm_len, unsigned long cbm)
}
/* CAT common functions implementation. */
+static char *feat_name[FEAT_TYPE_NUM] = {
+ "L3 CAT",
+ "CDP",
+ "L2 CAT",
+};
+
static int cat_init_feature(const struct cpuid_leaf *regs,
struct feat_node *feat,
struct psr_socket_info *info,
@@ -284,13 +292,17 @@ static int cat_init_feature(const struct cpuid_leaf *regs,
switch ( type )
{
case FEAT_TYPE_L3_CAT:
+ case FEAT_TYPE_L2_CAT:
if ( feat->cos_max < 1 )
return -ENOENT;
/* We reserve cos=0 as default cbm (all bits within cbm_len are 1). */
feat->cos_reg_val[0] = cat_default_val(feat->cbm_len);
- wrmsrl(MSR_IA32_PSR_L3_MASK(0), cat_default_val(feat->cbm_len));
+ wrmsrl((type == FEAT_TYPE_L3_CAT ?
+ MSR_IA32_PSR_L3_MASK(0) :
+ MSR_IA32_PSR_L2_MASK(0)),
+ cat_default_val(feat->cbm_len));
break;
@@ -328,8 +340,8 @@ static int cat_init_feature(const struct cpuid_leaf *regs,
return 0;
printk(XENLOG_INFO "%s: enabled on socket %u, cos_max:%u, cbm_len:%u\n",
- ((type == FEAT_TYPE_L3_CDP) ? "CDP" : "L3 CAT"),
- cpu_to_socket(smp_processor_id()), feat->cos_max, feat->cbm_len);
+ feat_name[type], cpu_to_socket(smp_processor_id()),
+ feat->cos_max, feat->cbm_len);
return 0;
}
@@ -390,6 +402,13 @@ static const struct feat_props l3_cdp_props = {
.write_msr = l3_cdp_write_msr,
};
+/* L2 CAT props */
+static const struct feat_props l2_cat_props = {
+ .cos_num = 1,
+ .type[0] = PSR_CBM_TYPE_L2,
+ .alt_type = PSR_CBM_TYPE_UNKNOWN,
+};
+
static void __init parse_psr_bool(char *s, char *value, char *feature,
unsigned int mask)
{
@@ -1345,6 +1364,10 @@ static int psr_cpu_prepare(void)
(feat_l3_cdp = xzalloc(struct feat_node)) == NULL )
return -ENOMEM;
+ if ( feat_l2_cat == NULL &&
+ (feat_l2_cat = xzalloc(struct feat_node)) == NULL )
+ return -ENOMEM;
+
return 0;
}
@@ -1392,6 +1415,17 @@ static void psr_cpu_init(void)
}
}
+ cpuid_count_leaf(PSR_CPUID_LEVEL_CAT, 0, ®s);
+ if ( regs.b & PSR_RESOURCE_TYPE_L2 )
+ {
+ cpuid_count_leaf(PSR_CPUID_LEVEL_CAT, 2, ®s);
+
+ feat = feat_l2_cat;
+ feat_l2_cat = NULL;
+ if ( !cat_init_feature(®s, feat, info, FEAT_TYPE_L2_CAT) )
+ feat_props[FEAT_TYPE_L2_CAT] = &l2_cat_props;
+ }
+
info->feat_init = true;
assoc_init:
@@ -345,6 +345,7 @@
#define MSR_IA32_PSR_L3_MASK(n) (0x00000c90 + (n))
#define MSR_IA32_PSR_L3_MASK_CODE(n) (0x00000c90 + (n) * 2 + 1)
#define MSR_IA32_PSR_L3_MASK_DATA(n) (0x00000c90 + (n) * 2)
+#define MSR_IA32_PSR_L2_MASK(n) (0x00000d10 + (n))
/* Intel Model 6 */
#define MSR_P6_PERFCTR(n) (0x000000c1 + (n))
@@ -23,6 +23,7 @@
/* Resource Type Enumeration */
#define PSR_RESOURCE_TYPE_L3 0x2
+#define PSR_RESOURCE_TYPE_L2 0x4
/* L3 Monitoring Features */
#define PSR_CMT_L3_OCCUPANCY 0x1
@@ -56,6 +57,7 @@ enum cbm_type {
PSR_CBM_TYPE_L3,
PSR_CBM_TYPE_L3_CODE,
PSR_CBM_TYPE_L3_DATA,
+ PSR_CBM_TYPE_L2,
PSR_CBM_TYPE_UNKNOWN,
};
This patch implements the CPU init flow for L2 CAT. Note: L2 CAT does NOT work until you apply the later patches of L2 CAT. "x86: L2 CAT: implement get hw info flow." "x86: L2 CAT: implement get value flow." "x86: L2 CAT: implement set value flow." Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com> --- v13: - add commit message. (suggested by Jan Beulich) - set 'alt_type' for L2 CAT. (suggested by Jan Beulich) - define a static string array to show which feature's info is printing. (suggested by Jan Beulich) v12: - move 'type[]' assignment into l2_cat_props declaration to make it be 'const'. (suggested by Jan Beulich) - add "L2 CAT" indicator in printk. (suggested by Jan Beulich) - restore mask(0) MSR to default value. (suggested by Jan Beulich) v11: - move l2 cat 'type[]' assignement into 'psr_cpu_init'. - remove COS MSR restore action in 'cpu_init_feature'. - set 'feat_init' to true after CPU init. - modify commit message. v10: - implement L2 CAT case in 'cat_init_feature'. (suggested by Jan Beulich) - changes about 'props'. (suggested by Jan Beulich) - introduce 'PSR_CBM_TYPE_L2'. v9: - modify error handling process in 'psr_cpu_prepare' to reduce redundant codes. - reuse 'cat_init_feature' and 'cat_get_cos_max' for L2 CAT to reduce redundant codes. (suggested by Roger Pau) - remove unnecessary comment. (suggested by Jan Beulich) - move L2 CAT related codes from 'cpu_init_work' into 'psr_cpu_init'. (suggested by Jan Beulich) - do not free resource when allocation fails in 'psr_cpu_prepare'. (suggested by Jan Beulich) v7: - initialize 'l2_cat'. (suggested by Konrad Rzeszutek Wilk) v6: - use 'struct cpuid_leaf'. (suggested by Konrad Rzeszutek Wilk and Jan Beulich) v5: - remove 'feat_l2_cat' free in 'free_feature'. (suggested by Jan Beulich) - encapsulate cpuid registers into 'struct cpuid_leaf_regs'. (suggested by Jan Beulich) - print socket info when 'opt_cpu_info' is true. (suggested by Jan Beulich) - rename 'l2_cat_get_max_cos_max' to 'l2_cat_get_cos_max'. (suggested by Jan Beulich) - rename 'dat[]' to 'data[]' (suggested by Jan Beulich) - move 'cpu_prepare_work' contents into 'psr_cpu_prepare'. (suggested by Jan Beulich) v4: - create this patch because of codes architecture change. (suggested by Jan Beulich) --- xen/arch/x86/psr.c | 40 +++++++++++++++++++++++++++++++++++++--- xen/include/asm-x86/msr-index.h | 1 + xen/include/asm-x86/psr.h | 2 ++ 3 files changed, 40 insertions(+), 3 deletions(-)