| Message ID | 1498127402-6705-2-git-send-email-frank.wang@rock-chips.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Am Donnerstag, 22. Juni 2017, 18:29:56 CEST schrieb Frank Wang: > This patch sets PSCI as the default cpu enable-method for RK3228 SoC. > > Signed-off-by: Frank Wang <frank.wang@rock-chips.com> I've seen the work on OP-TEE mainlining for the psci implementation which seems to be progressing nicely and with the code in the open now, it's possible to replace the firmware if needed. So I've applied this patch for 4.14. Heiko -- To unsubscribe from this list: send the line "unsubscribe linux-mmc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi index 31e04e9..34d175e 100644 --- a/arch/arm/boot/dts/rk322x.dtsi +++ b/arch/arm/boot/dts/rk322x.dtsi @@ -70,6 +70,7 @@ #cooling-cells = <2>; /* min followed by max */ clock-latency = <40000>; clocks = <&cru ARMCLK>; + enable-method = "psci"; }; cpu1: cpu@f01 { @@ -78,6 +79,7 @@ reg = <0xf01>; resets = <&cru SRST_CORE1>; operating-points-v2 = <&cpu0_opp_table>; + enable-method = "psci"; }; cpu2: cpu@f02 { @@ -86,6 +88,7 @@ reg = <0xf02>; resets = <&cru SRST_CORE2>; operating-points-v2 = <&cpu0_opp_table>; + enable-method = "psci"; }; cpu3: cpu@f03 { @@ -94,6 +97,7 @@ reg = <0xf03>; resets = <&cru SRST_CORE3>; operating-points-v2 = <&cpu0_opp_table>; + enable-method = "psci"; }; }; @@ -151,6 +155,11 @@ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; }; + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + }; + timer { compatible = "arm,armv7-timer"; arm,cpu-registers-not-fw-configured;
This patch sets PSCI as the default cpu enable-method for RK3228 SoC. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> --- arch/arm/boot/dts/rk322x.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+)