| Message ID | 1490355764-17230-1-git-send-email-praveen.paneri@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Em Sex, 2017-03-24 às 17:12 +0530, Praveen Paneri escreveu: > When FBC is enabled for linear, legacy Y-tiled and Yf-tiled > surfaces on gen9, the cfb stride must be programmed by SW as > > cfb_stride = ceiling[(at least plane width in pixels)/ > (32 * compression limit factor)] * 8 > > v2: Minor fix for a build error > > v3: Fixed subject, register name and platform check (Ville) > > v4: Added WA details in comment (Paulo) > > Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > Signed-off-by: Praveen Paneri <praveen.paneri@intel.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 3 +++ > drivers/gpu/drm/i915/intel_fbc.c | 9 +++++++++ > 2 files changed, 12 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h > b/drivers/gpu/drm/i915/i915_reg.h > index 04c8f69..4adf2e6 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -6504,6 +6504,9 @@ enum { > #define GLK_CL1_PWR_DOWN (1 << 11) > #define GLK_CL2_PWR_DOWN (1 << 12) > > +#define CHICKEN_MISC_4 _MMIO(0x4208c) > +#define FBC_STRIDE_OVERRIDE (1<<13) > + > #define _CHICKEN_PIPESL_1_A 0x420b0 > #define _CHICKEN_PIPESL_1_B 0x420b4 > #define HSW_FBCQ_DIS (1 << 22) > diff --git a/drivers/gpu/drm/i915/intel_fbc.c > b/drivers/gpu/drm/i915/intel_fbc.c > index ded2add..1183633 100644 > --- a/drivers/gpu/drm/i915/intel_fbc.c > +++ b/drivers/gpu/drm/i915/intel_fbc.c > @@ -298,9 +298,18 @@ static bool ilk_fbc_is_active(struct > drm_i915_private *dev_priv) > static void gen7_fbc_activate(struct drm_i915_private *dev_priv) > { > struct intel_fbc_reg_params *params = &dev_priv->fbc.params; > + struct intel_fbc_state_cache *cache = &dev_priv- > >fbc.state_cache; Please take a look at b183b3f14395. We need to store the calculated stride value in reg_params so the stride value can actually be taken into consideration when comparing different FBC configurations. > u32 dpfc_ctl; > int threshold = dev_priv->fbc.threshold; > > + /* Display WA #0529: skl, kbl, bxt, glk */ > + if (IS_GEN9(dev_priv) && AFAIU, this WA shouldn't be applied for GLK. > + i915_gem_object_get_tiling(cache->vma->obj) != > I915_TILING_X) { > + int cfb_stride = DIV_ROUND_UP(cache->plane.src_w, > + (32 * threshold)) * 8; > + I915_WRITE(CHICKEN_MISC_4, FBC_STRIDE_OVERRIDE | > cfb_stride); We need to zero those bits when we're not using Y tiling. I mean, at least bit 13. Also, CHICKEN_MISC_4 contains other fields not touched here, so we should probably do a read-modify-write on it, preserving everything we're not touching. Thanks, Paulo > + } > + > dpfc_ctl = 0; > if (IS_IVYBRIDGE(dev_priv)) > dpfc_ctl |= IVB_DPFC_CTL_PLANE(params->crtc.plane);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 04c8f69..4adf2e6 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6504,6 +6504,9 @@ enum { #define GLK_CL1_PWR_DOWN (1 << 11) #define GLK_CL2_PWR_DOWN (1 << 12) +#define CHICKEN_MISC_4 _MMIO(0x4208c) +#define FBC_STRIDE_OVERRIDE (1<<13) + #define _CHICKEN_PIPESL_1_A 0x420b0 #define _CHICKEN_PIPESL_1_B 0x420b4 #define HSW_FBCQ_DIS (1 << 22) diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c index ded2add..1183633 100644 --- a/drivers/gpu/drm/i915/intel_fbc.c +++ b/drivers/gpu/drm/i915/intel_fbc.c @@ -298,9 +298,18 @@ static bool ilk_fbc_is_active(struct drm_i915_private *dev_priv) static void gen7_fbc_activate(struct drm_i915_private *dev_priv) { struct intel_fbc_reg_params *params = &dev_priv->fbc.params; + struct intel_fbc_state_cache *cache = &dev_priv->fbc.state_cache; u32 dpfc_ctl; int threshold = dev_priv->fbc.threshold; + /* Display WA #0529: skl, kbl, bxt, glk */ + if (IS_GEN9(dev_priv) && + i915_gem_object_get_tiling(cache->vma->obj) != I915_TILING_X) { + int cfb_stride = DIV_ROUND_UP(cache->plane.src_w, + (32 * threshold)) * 8; + I915_WRITE(CHICKEN_MISC_4, FBC_STRIDE_OVERRIDE | cfb_stride); + } + dpfc_ctl = 0; if (IS_IVYBRIDGE(dev_priv)) dpfc_ctl |= IVB_DPFC_CTL_PLANE(params->crtc.plane);
When FBC is enabled for linear, legacy Y-tiled and Yf-tiled surfaces on gen9, the cfb stride must be programmed by SW as cfb_stride = ceiling[(at least plane width in pixels)/ (32 * compression limit factor)] * 8 v2: Minor fix for a build error v3: Fixed subject, register name and platform check (Ville) v4: Added WA details in comment (Paulo) Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Praveen Paneri <praveen.paneri@intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 3 +++ drivers/gpu/drm/i915/intel_fbc.c | 9 +++++++++ 2 files changed, 12 insertions(+)