diff mbox

drm/i915/cnl: Fix loadgen select programming on ddi vswing sequence

Message ID 1500329122-32662-1-git-send-email-manasi.d.navare@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Navare, Manasi July 17, 2017, 10:05 p.m. UTC
The condition for setting the Loadgen Select bit of
PORT_TX_DW4 register during DDI Vswing Sequence should be
Bit rate <=6 GHz whereas the existing code checks only
Bit Rate < 6GHz. This patch fixes this condition.
While at it also remove the redundant paranthesis.

Fixes: cf54ca8bc567 ("drm/i915/cnl: Implement voltage swing sequence.")
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

Comments

Zanoni, Paulo R July 25, 2017, 5:38 p.m. UTC | #1
Em Seg, 2017-07-17 às 15:05 -0700, Manasi Navare escreveu:
> The condition for setting the Loadgen Select bit of
> PORT_TX_DW4 register during DDI Vswing Sequence should be
> Bit rate <=6 GHz whereas the existing code checks only
> Bit Rate < 6GHz. This patch fixes this condition.
> While at it also remove the redundant paranthesis.
> 
> Fixes: cf54ca8bc567 ("drm/i915/cnl: Implement voltage swing
> sequence.")
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_ddi.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> b/drivers/gpu/drm/i915/intel_ddi.c
> index efb1358..f4fbb39 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -2010,8 +2010,8 @@ static void cnl_ddi_vswing_sequence(struct
> intel_encoder *encoder, u32 level)
>  		val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
>  		val &= ~LOADGEN_SELECT;
>  
> -		if (((rate < 600000) && (width == 4) && (ln >=
> 1))  ||
> -		    ((rate < 600000) && (width < 4) && ((ln == 1) ||
> (ln == 2)))) {
> +		if ((rate <= 600000 && width == 4 && ln >= 1)  ||
> +		    (rate <= 600000 && width < 4 && (ln == 1 || ln
> == 2))) {
>  			val |= LOADGEN_SELECT;
>  		}
>  		I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val);
Navare, Manasi July 25, 2017, 6:24 p.m. UTC | #2
Thanks for the review !

Manasi


Em Seg, 2017-07-17 às 15:05 -0700, Manasi Navare escreveu:
> The condition for setting the Loadgen Select bit of

> PORT_TX_DW4 register during DDI Vswing Sequence should be Bit rate <=6 

> GHz whereas the existing code checks only Bit Rate < 6GHz. This patch 

> fixes this condition.

> While at it also remove the redundant paranthesis.

> 

> Fixes: cf54ca8bc567 ("drm/i915/cnl: Implement voltage swing

> sequence.")

> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>

> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>

> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>


Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>


> ---

>  drivers/gpu/drm/i915/intel_ddi.c | 4 ++--

>  1 file changed, 2 insertions(+), 2 deletions(-)

> 

> diff --git a/drivers/gpu/drm/i915/intel_ddi.c

> b/drivers/gpu/drm/i915/intel_ddi.c

> index efb1358..f4fbb39 100644

> --- a/drivers/gpu/drm/i915/intel_ddi.c

> +++ b/drivers/gpu/drm/i915/intel_ddi.c

> @@ -2010,8 +2010,8 @@ static void cnl_ddi_vswing_sequence(struct 

> intel_encoder *encoder, u32 level)

>  		val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));

>  		val &= ~LOADGEN_SELECT;

>  

> -		if (((rate < 600000) && (width == 4) && (ln >=

> 1))  ||

> -		    ((rate < 600000) && (width < 4) && ((ln == 1) ||

> (ln == 2)))) {

> +		if ((rate <= 600000 && width == 4 && ln >= 1)  ||

> +		    (rate <= 600000 && width < 4 && (ln == 1 || ln

> == 2))) {

>  			val |= LOADGEN_SELECT;

>  		}

>  		I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val);
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index efb1358..f4fbb39 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2010,8 +2010,8 @@  static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder, u32 level)
 		val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
 		val &= ~LOADGEN_SELECT;
 
-		if (((rate < 600000) && (width == 4) && (ln >= 1))  ||
-		    ((rate < 600000) && (width < 4) && ((ln == 1) || (ln == 2)))) {
+		if ((rate <= 600000 && width == 4 && ln >= 1)  ||
+		    (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
 			val |= LOADGEN_SELECT;
 		}
 		I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val);