| Message ID | 1501010261-7130-1-git-send-email-sergej@taudac.com (mailing list archive) |
|---|---|
| State | Rejected |
| Delegated to: | Stephen Boyd |
| Headers | show |
On 07/25, Sergej Sawazki wrote: > The "Si5351A/B/C Data Sheet" states to apply a PLLA and PLLB soft reset > before enabling the outputs [1]. This is required to get a deterministic > phase relationship between the output clocks. > > Without the PLL reset, the phase offset beween the clocks is unpredictable. > > References: > [1] https://www.silabs.com/Support%20Documents/TechnicalDocs/Si5351-B.pdf > Figure 12 ("I2C Programming Procedure") > > Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> > Cc: Rabeeh Khoury <rabeeh@solid-run.com> > Signed-off-by: Sergej Sawazki <sergej@taudac.com> > --- This is similar to commit 6dc669a22c77 (clk: si5351: Add PLL soft reset, 2015-11-20)? But I think that commit was causing some problem for Russell King and there was going to be a patch to change it but nothing has materialized on the list. Unless this is that patch? Does the other reset in this driver need to be removed? At the least, it may be a good idea to combine the two places where CLK_POWERDOWN is cleared to also have this reset part. > drivers/clk/clk-si5351.c | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/drivers/clk/clk-si5351.c b/drivers/clk/clk-si5351.c > index 255d0fe..6cca425 100644 > --- a/drivers/clk/clk-si5351.c > +++ b/drivers/clk/clk-si5351.c > @@ -905,6 +905,15 @@ static int si5351_clkout_prepare(struct clk_hw *hw) > > si5351_set_bits(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num, > SI5351_CLK_POWERDOWN, 0); > + > + /* > + * Reset the PLLs before enabling the outputs to get a deterministic > + * phase relationship between the output clocks. Otherwise, the phase > + * offset beween the clocks is unpredictable. > + */ > + si5351_reg_write(hwdata->drvdata, SI5351_PLL_RESET, > + SI5351_PLL_RESET_A | SI5351_PLL_RESET_B); > + > si5351_set_bits(hwdata->drvdata, SI5351_OUTPUT_ENABLE_CTRL, > (1 << hwdata->num), 0); > return 0;
On 26.07.2017 03:11, Stephen Boyd wrote: > On 07/25, Sergej Sawazki wrote: >> The "Si5351A/B/C Data Sheet" states to apply a PLLA and PLLB soft reset >> before enabling the outputs [1]. This is required to get a deterministic >> phase relationship between the output clocks. >> >> Without the PLL reset, the phase offset beween the clocks is unpredictable. >> >> References: >> [1] https://www.silabs.com/Support%20Documents/TechnicalDocs/Si5351-B.pdf >> Figure 12 ("I2C Programming Procedure") >> >> Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> >> Cc: Rabeeh Khoury <rabeeh@solid-run.com> >> Signed-off-by: Sergej Sawazki <sergej@taudac.com> >> --- > > This is similar to commit 6dc669a22c77 (clk: si5351: Add PLL soft > reset, 2015-11-20)? But I think that commit was causing some > problem for Russell King and there was going to be a patch to > change it but nothing has materialized on the list. Unless this > is that patch? Sergej, Stephen, resetting both PLLs in this driver will not happen as it does have an influence on the other PLL and all clocks on it. I understand that some of the functions of the clk gen will not be available with this driver but it is not the use case of this driver. So, NAK on this one. The patch you are talking about is still pending but I think I just send it in a few days. Sebastian > Does the other reset in this driver need to be removed? At the > least, it may be a good idea to combine the two places where > CLK_POWERDOWN is cleared to also have this reset part. > >> drivers/clk/clk-si5351.c | 9 +++++++++ >> 1 file changed, 9 insertions(+) >> >> diff --git a/drivers/clk/clk-si5351.c b/drivers/clk/clk-si5351.c >> index 255d0fe..6cca425 100644 >> --- a/drivers/clk/clk-si5351.c >> +++ b/drivers/clk/clk-si5351.c >> @@ -905,6 +905,15 @@ static int si5351_clkout_prepare(struct clk_hw *hw) >> >> si5351_set_bits(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num, >> SI5351_CLK_POWERDOWN, 0); >> + >> + /* >> + * Reset the PLLs before enabling the outputs to get a deterministic >> + * phase relationship between the output clocks. Otherwise, the phase >> + * offset beween the clocks is unpredictable. >> + */ >> + si5351_reg_write(hwdata->drvdata, SI5351_PLL_RESET, >> + SI5351_PLL_RESET_A | SI5351_PLL_RESET_B); >> + >> si5351_set_bits(hwdata->drvdata, SI5351_OUTPUT_ENABLE_CTRL, >> (1 << hwdata->num), 0); >> return 0; > -- To unsubscribe from this list: send the line "unsubscribe linux-clk" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Sorry for the HTML stuff in my previous message, please ignore it. Am 26.07.2017 um 06:43 schrieb Sebastian Hesselbarth: > On 26.07.2017 03:11, Stephen Boyd wrote: >> On 07/25, Sergej Sawazki wrote: >>> The "Si5351A/B/C Data Sheet" states to apply a PLLA and PLLB soft reset >>> before enabling the outputs [1]. This is required to get a deterministic >>> phase relationship between the output clocks. >>> >>> Without the PLL reset, the phase offset beween the clocks is unpredictable. >>> >>> References: >>> [1] https://www.silabs.com/Support%20Documents/TechnicalDocs/Si5351-B.pdf >>> Figure 12 ("I2C Programming Procedure") >>> >>> Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> >>> Cc: Rabeeh Khoury <rabeeh@solid-run.com> >>> Signed-off-by: Sergej Sawazki <sergej@taudac.com> >>> --- >> This is similar to commit 6dc669a22c77 (clk: si5351: Add PLL soft >> reset, 2015-11-20)? But I think that commit was causing some >> problem for Russell King and there was going to be a patch to >> change it but nothing has materialized on the list. Unless this >> is that patch? > Sergej, Stephen, > > resetting both PLLs in this driver will not happen as it does have > an influence on the other PLL and all clocks on it. > > I understand that some of the functions of the clk gen will not be > available with this driver but it is not the use case of this driver. > > So, NAK on this one. > > The patch you are talking about is still pending but I think I just > send it in a few days. > > Sebastian > Sebastian, Stephen, On my setup, the Si5351 provides audio bit and frame clocks. Without resetting the PLLs before enabling the output clocks the phase offset between the clocks is unpredictable, the clocks are not aligned, this corrupts the audio stream. I agree, resetting both PLLs is not a good idea. Only one PLL should be resetted (the one that the output clocks are connected to). I am not changing the rates, I am only enabling/disabling the outputs and changing the clkin source. So resetting the PLL in set_rate() does not help me. Sergej -- To unsubscribe from this list: send the line "unsubscribe linux-clk" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Thu, Jul 27, 2017 at 01:10:58AM +0200, Sergej Sawazki wrote: > Am 26.07.2017 um 06:43 schrieb Sebastian Hesselbarth: > > On 26.07.2017 03:11, Stephen Boyd wrote: > >> On 07/25, Sergej Sawazki wrote: > >>> The "Si5351A/B/C Data Sheet" states to apply a PLLA and PLLB soft reset > >>> before enabling the outputs [1]. This is required to get a deterministic > >>> phase relationship between the output clocks. > >>> > >>> Without the PLL reset, the phase offset beween the clocks is unpredictable. > >>> > >>> References: > >>> [1] https://www.silabs.com/Support%20Documents/TechnicalDocs/Si5351-B.pdf > >>> Figure 12 ("I2C Programming Procedure") > >>> > >>> Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> > >>> Cc: Rabeeh Khoury <rabeeh@solid-run.com> > >>> Signed-off-by: Sergej Sawazki <sergej@taudac.com> > >>> --- > >> This is similar to commit 6dc669a22c77 (clk: si5351: Add PLL soft > >> reset, 2015-11-20)? But I think that commit was causing some > >> problem for Russell King and there was going to be a patch to > >> change it but nothing has materialized on the list. Unless this > >> is that patch? > > Sergej, Stephen, > > > > resetting both PLLs in this driver will not happen as it does have > > an influence on the other PLL and all clocks on it. > > > > I understand that some of the functions of the clk gen will not be > > available with this driver but it is not the use case of this driver. > > > > So, NAK on this one. > > > > The patch you are talking about is still pending but I think I just > > send it in a few days. > > > > Sebastian > > Sebastian, Stephen, > > On my setup, the Si5351 provides audio bit and frame clocks. Without > resetting the PLLs before enabling the output clocks the phase offset > between the clocks is unpredictable, the clocks are not aligned, this > corrupts the audio stream. > > I agree, resetting both PLLs is not a good idea. Only one PLL should > be resetted (the one that the output clocks are connected to). > > I am not changing the rates, I am only enabling/disabling the outputs > and changing the clkin source. So resetting the PLL in set_rate() does > not help me. However you may wish to do this, you must not do it in a way that regresses other platforms. In other words, if you need to reset both PLLs, and that disrupts other platforms, resetting the PLLs needs to be configurable by some mechanism, so the platforms that need it can have it, but those that don't (and are positively harmed by it) need it can remain unaffected.
On 27.07.2017 11:11, Russell King - ARM Linux wrote: > On Thu, Jul 27, 2017 at 01:10:58AM +0200, Sergej Sawazki wrote: >> Am 26.07.2017 um 06:43 schrieb Sebastian Hesselbarth: >>> On 26.07.2017 03:11, Stephen Boyd wrote: >>>> On 07/25, Sergej Sawazki wrote: >>>>> The "Si5351A/B/C Data Sheet" states to apply a PLLA and PLLB soft reset >>>>> before enabling the outputs [1]. This is required to get a deterministic >>>>> phase relationship between the output clocks. >>>>> >>>>> Without the PLL reset, the phase offset beween the clocks is unpredictable. [...] >>> >>> resetting both PLLs in this driver will not happen as it does have >>> an influence on the other PLL and all clocks on it. >>> >>> I understand that some of the functions of the clk gen will not be >>> available with this driver but it is not the use case of this driver. >>> >>> So, NAK on this one. >>> >>> The patch you are talking about is still pending but I think I just >>> send it in a few days. >> >> On my setup, the Si5351 provides audio bit and frame clocks. Without >> resetting the PLLs before enabling the output clocks the phase offset >> between the clocks is unpredictable, the clocks are not aligned, this >> corrupts the audio stream. Sergej, if the two clocks you are generating are directly related to each other. why aren't you using _one_ PLL and derive both clocks from the same PLL? This should solve your alignment issues. >> I agree, resetting both PLLs is not a good idea. Only one PLL should >> be resetted (the one that the output clocks are connected to). >> >> I am not changing the rates, I am only enabling/disabling the outputs >> and changing the clkin source. So resetting the PLL in set_rate() does >> not help me. > > However you may wish to do this, you must not do it in a way that > regresses other platforms. > > In other words, if you need to reset both PLLs, and that disrupts > other platforms, resetting the PLLs needs to be configurable by > some mechanism, so the platforms that need it can have it, but > those that don't (and are positively harmed by it) need it can > remain unaffected. I copy that. If there is the need for resetting both PLLs, we do need another DT property that tells the driver to do so. Resetting both PLLs does interrupt all clocks and that does cause a regression on systems where clocks derived from both PLLs do different things. Sebastian -- To unsubscribe from this list: send the line "unsubscribe linux-clk" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Am 28.07.2017 um 09:33 schrieb Sebastian Hesselbarth: > On 27.07.2017 11:11, Russell King - ARM Linux wrote: >> On Thu, Jul 27, 2017 at 01:10:58AM +0200, Sergej Sawazki wrote: >>> Am 26.07.2017 um 06:43 schrieb Sebastian Hesselbarth:[...] >>> On my setup, the Si5351 provides audio bit and frame clocks. Without >>> resetting the PLLs before enabling the output clocks the phase offset >>> between the clocks is unpredictable, the clocks are not aligned, this >>> corrupts the audio stream. > > Sergej, > > if the two clocks you are generating are directly related to each other. > why aren't you using _one_ PLL and derive both clocks from the same PLL? > > This should solve your alignment issues. > [...] Sebastian, I am using _one_ PLL for all my clocks, still, the phase relationship between the clocks is random on each activation. The only way I was able to fix it, is to reset the corresponding PLL. Sergej -- To unsubscribe from this list: send the line "unsubscribe linux-clk" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/drivers/clk/clk-si5351.c b/drivers/clk/clk-si5351.c index 255d0fe..6cca425 100644 --- a/drivers/clk/clk-si5351.c +++ b/drivers/clk/clk-si5351.c @@ -905,6 +905,15 @@ static int si5351_clkout_prepare(struct clk_hw *hw) si5351_set_bits(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num, SI5351_CLK_POWERDOWN, 0); + + /* + * Reset the PLLs before enabling the outputs to get a deterministic + * phase relationship between the output clocks. Otherwise, the phase + * offset beween the clocks is unpredictable. + */ + si5351_reg_write(hwdata->drvdata, SI5351_PLL_RESET, + SI5351_PLL_RESET_A | SI5351_PLL_RESET_B); + si5351_set_bits(hwdata->drvdata, SI5351_OUTPUT_ENABLE_CTRL, (1 << hwdata->num), 0); return 0;
The "Si5351A/B/C Data Sheet" states to apply a PLLA and PLLB soft reset before enabling the outputs [1]. This is required to get a deterministic phase relationship between the output clocks. Without the PLL reset, the phase offset beween the clocks is unpredictable. References: [1] https://www.silabs.com/Support%20Documents/TechnicalDocs/Si5351-B.pdf Figure 12 ("I2C Programming Procedure") Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Cc: Rabeeh Khoury <rabeeh@solid-run.com> Signed-off-by: Sergej Sawazki <sergej@taudac.com> --- drivers/clk/clk-si5351.c | 9 +++++++++ 1 file changed, 9 insertions(+)