| Message ID | 1501304340-27452-1-git-send-email-praveen.paneri@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Sat, Jul 29, 2017 at 10:29:00AM +0530, Praveen Paneri wrote: > This WA is required when decopled frequencies for slice > and unslice are enabled. This disables DOP clock gating > for SKL GT4. > > Cc: David Weinehall <david.weinehall@linux.intel.com> > Signed-off-by: Praveen Paneri <praveen.paneri@intel.com> Tested to fix hangs on GT4; I would suggest applying this fix for all GEN 9 platforms though, not just SKL GT4e, even if that platform is the only one where we've been able to trigger the issue so far. Anyway, the fix works and is correct, so: Reviewed-by: David Weinehall <david.weinehall@linux.intel.com> > --- > drivers/gpu/drm/i915/intel_pm.c | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 48785ef..6dee3b6 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -78,6 +78,12 @@ static void gen9_init_clock_gating(struct drm_i915_private *dev_priv) > /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl,cfl */ > I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) | > ILK_DPFC_DISABLE_DUMMY0); > + > + if (IS_SKL_GT4(dev_priv)) { > + /* WaDisableDopClockGating */ > + I915_WRITE(GEN7_MISCCPCTL, I915_READ(GEN7_MISCCPCTL) > + & ~GEN7_DOP_CLOCK_GATE_ENABLE); > + } > } > > static void bxt_init_clock_gating(struct drm_i915_private *dev_priv) > -- > 1.9.1 >
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 48785ef..6dee3b6 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -78,6 +78,12 @@ static void gen9_init_clock_gating(struct drm_i915_private *dev_priv) /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl,cfl */ I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) | ILK_DPFC_DISABLE_DUMMY0); + + if (IS_SKL_GT4(dev_priv)) { + /* WaDisableDopClockGating */ + I915_WRITE(GEN7_MISCCPCTL, I915_READ(GEN7_MISCCPCTL) + & ~GEN7_DOP_CLOCK_GATE_ENABLE); + } } static void bxt_init_clock_gating(struct drm_i915_private *dev_priv)
This WA is required when decopled frequencies for slice and unslice are enabled. This disables DOP clock gating for SKL GT4. Cc: David Weinehall <david.weinehall@linux.intel.com> Signed-off-by: Praveen Paneri <praveen.paneri@intel.com> --- drivers/gpu/drm/i915/intel_pm.c | 6 ++++++ 1 file changed, 6 insertions(+)