| Message ID | 1502956490-23087-2-git-send-email-william.wu@rock-chips.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Hi William, Am Donnerstag, 17. August 2017, 15:54:49 CEST schrieb William Wu: > RK3328 has one USB 3.0 OTG controller which uses DWC_USB3 > core's general architecture. It can act as static xHCI host > controller, static device controller, USB 3.0/2.0 OTG basing > on ID of USB3.0 PHY. > > Signed-off-by: William Wu <william.wu@rock-chips.com> > --- > Changes in v2: > - Modify the dwc3 quirk "snps,tx-ipgap-linecheck-dis-quirk" to > "snps,dis-tx-ipgap-linecheck-quirk" > > .../devicetree/bindings/usb/rockchip,dwc3.txt | 4 +++- > arch/arm64/boot/dts/rockchip/rk3328.dtsi | 27 ++++++++++++++++++++++ > 2 files changed, 30 insertions(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/usb/rockchip,dwc3.txt b/Documentation/devicetree/bindings/usb/rockchip,dwc3.txt > index 0536a93..d6b2e47 100644 > --- a/Documentation/devicetree/bindings/usb/rockchip,dwc3.txt > +++ b/Documentation/devicetree/bindings/usb/rockchip,dwc3.txt > @@ -1,7 +1,9 @@ > Rockchip SuperSpeed DWC3 USB SoC controller > > Required properties: > -- compatible: should contain "rockchip,rk3399-dwc3" for rk3399 SoC > +- compatible: should be one of the following: > + - "rockchip,rk3399-dwc3": for rk3399 SoC > + - "rockchip,rk3328-dwc3", "rockchip,rk3399-dwc3": for rk3328 SoC > - clocks: A list of phandle + clock-specifier pairs for the > clocks listed in clock-names > - clock-names: Should contain the following: This probably shouldn't be part of the patch adding the dts node, but instead should be a separate patch and should either go through some usb tree or at least get an Ack from usb maintainers (Felipe Balbi and/or Greg Kroah Hartman), so you should definitly include them into your recipient list. Heiko
Dear Heiko, 在 2017年08月18日 17:24, Heiko Stuebner 写道: > Hi William, > > Am Donnerstag, 17. August 2017, 15:54:49 CEST schrieb William Wu: >> RK3328 has one USB 3.0 OTG controller which uses DWC_USB3 >> core's general architecture. It can act as static xHCI host >> controller, static device controller, USB 3.0/2.0 OTG basing >> on ID of USB3.0 PHY. >> >> Signed-off-by: William Wu <william.wu@rock-chips.com> >> --- >> Changes in v2: >> - Modify the dwc3 quirk "snps,tx-ipgap-linecheck-dis-quirk" to >> "snps,dis-tx-ipgap-linecheck-quirk" >> >> .../devicetree/bindings/usb/rockchip,dwc3.txt | 4 +++- >> arch/arm64/boot/dts/rockchip/rk3328.dtsi | 27 ++++++++++++++++++++++ >> 2 files changed, 30 insertions(+), 1 deletion(-) >> >> diff --git a/Documentation/devicetree/bindings/usb/rockchip,dwc3.txt b/Documentation/devicetree/bindings/usb/rockchip,dwc3.txt >> index 0536a93..d6b2e47 100644 >> --- a/Documentation/devicetree/bindings/usb/rockchip,dwc3.txt >> +++ b/Documentation/devicetree/bindings/usb/rockchip,dwc3.txt >> @@ -1,7 +1,9 @@ >> Rockchip SuperSpeed DWC3 USB SoC controller >> >> Required properties: >> -- compatible: should contain "rockchip,rk3399-dwc3" for rk3399 SoC >> +- compatible: should be one of the following: >> + - "rockchip,rk3399-dwc3": for rk3399 SoC >> + - "rockchip,rk3328-dwc3", "rockchip,rk3399-dwc3": for rk3328 SoC >> - clocks: A list of phandle + clock-specifier pairs for the >> clocks listed in clock-names >> - clock-names: Should contain the following: > This probably shouldn't be part of the patch adding the dts node, but > instead should be a separate patch and should either go through some > usb tree or at least get an Ack from usb maintainers (Felipe Balbi and/or > Greg Kroah Hartman), so you should definitly include them into your > recipient list. Thanks for your suggestion. I will submit two patches separately, and add usb maintainers in the recipient list. > > > Heiko > > > >
diff --git a/Documentation/devicetree/bindings/usb/rockchip,dwc3.txt b/Documentation/devicetree/bindings/usb/rockchip,dwc3.txt index 0536a93..d6b2e47 100644 --- a/Documentation/devicetree/bindings/usb/rockchip,dwc3.txt +++ b/Documentation/devicetree/bindings/usb/rockchip,dwc3.txt @@ -1,7 +1,9 @@ Rockchip SuperSpeed DWC3 USB SoC controller Required properties: -- compatible: should contain "rockchip,rk3399-dwc3" for rk3399 SoC +- compatible: should be one of the following: + - "rockchip,rk3399-dwc3": for rk3399 SoC + - "rockchip,rk3328-dwc3", "rockchip,rk3399-dwc3": for rk3328 SoC - clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock-names - clock-names: Should contain the following: diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi index e6da0ce..14bd8f4 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi @@ -655,6 +655,33 @@ status = "disabled"; }; + usbdrd3: usb@ff600000 { + compatible = "rockchip,rk3328-dwc3", "rockchip,rk3399-dwc3"; + clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>, + <&cru ACLK_USB3OTG>; + clock-names = "ref_clk", "suspend_clk", + "bus_clk"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + usbdrd_dwc3: dwc3@ff600000 { + compatible = "snps,dwc3"; + reg = <0x0 0xff600000 0x0 0x100000>; + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; + dr_mode = "otg"; + phy_type = "utmi_wide"; + snps,dis_enblslpm_quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + status = "disabled"; + }; + }; + gic: interrupt-controller@ff811000 { compatible = "arm,gic-400"; #interrupt-cells = <3>;
RK3328 has one USB 3.0 OTG controller which uses DWC_USB3 core's general architecture. It can act as static xHCI host controller, static device controller, USB 3.0/2.0 OTG basing on ID of USB3.0 PHY. Signed-off-by: William Wu <william.wu@rock-chips.com> --- Changes in v2: - Modify the dwc3 quirk "snps,tx-ipgap-linecheck-dis-quirk" to "snps,dis-tx-ipgap-linecheck-quirk" .../devicetree/bindings/usb/rockchip,dwc3.txt | 4 +++- arch/arm64/boot/dts/rockchip/rk3328.dtsi | 27 ++++++++++++++++++++++ 2 files changed, 30 insertions(+), 1 deletion(-)