| Message ID | 20170912210523.663877115@cogentembedded.com (mailing list archive) |
|---|---|
| State | Changes Requested |
| Delegated to: | Simon Horman |
| Headers | show |
Hi Sergei, On Tue, Sep 12, 2017 at 10:37 PM, Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> wrote: > The initial R8A77970 SoC device tree including Cortex-A53 CPU, GIC, timer, > CPG, RST, and SYSC. > > Based on the original (and large) patch by Daisuke Matsushita > <daisuke.matsushita.ns@hitachi.com>. > > Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> > Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> > > --- > arch/arm64/boot/dts/renesas/r8a77970.dtsi | 126 ++++++++++++++++++++++++++++++ > 1 file changed, 126 insertions(+) > > Index: renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi > =================================================================== > --- /dev/null > +++ renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi > @@ -0,0 +1,126 @@ > +/* > + * Device Tree Source for the r8a77970 SoC > + * > + * Copyright (C) 2016-2017 Renesas Electronics Corp. > + * Copyright (C) 2017 Cogent Embedded, Inc. > + * > + * This file is licensed under the terms of the GNU General Public License > + * version 2. This program is licensed "as is" without any warranty of any > + * kind, whether express or implied. > + */ > + > +#include <dt-bindings/interrupt-controller/irq.h> > +#include <dt-bindings/interrupt-controller/arm-gic.h> arm-gic.h includes irq.h. > +#include <dt-bindings/clock/renesas-cpg-mssr.h> > +#include <dt-bindings/power/r8a77970-sysc.h> You can avoid the dependency on the above header, which will go upstream through a different branch, by hardcoding the power area indices for the initial submission, like you already did for the CPG core clocks. > + > +/ { > + compatible = "renesas,r8a77970"; > + #address-cells = <2>; > + #size-cells = <2>; > + > + psci { > + compatible = "arm,psci-1.0"; PSCI 1.0 is backwards compatible with PSI 0.2: compatible = "arm,psci-1.0", "arm,psci-0.2"; Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
On 09/13/2017 11:59 AM, Geert Uytterhoeven wrote: >> The initial R8A77970 SoC device tree including Cortex-A53 CPU, GIC, timer, >> CPG, RST, and SYSC. >> >> Based on the original (and large) patch by Daisuke Matsushita >> <daisuke.matsushita.ns@hitachi.com>. >> >> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> >> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> >> >> --- >> arch/arm64/boot/dts/renesas/r8a77970.dtsi | 126 ++++++++++++++++++++++++++++++ >> 1 file changed, 126 insertions(+) >> >> Index: renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi >> =================================================================== >> --- /dev/null >> +++ renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi >> @@ -0,0 +1,126 @@ >> +/* >> + * Device Tree Source for the r8a77970 SoC >> + * >> + * Copyright (C) 2016-2017 Renesas Electronics Corp. >> + * Copyright (C) 2017 Cogent Embedded, Inc. >> + * >> + * This file is licensed under the terms of the GNU General Public License >> + * version 2. This program is licensed "as is" without any warranty of any >> + * kind, whether express or implied. >> + */ >> + >> +#include <dt-bindings/interrupt-controller/irq.h> >> +#include <dt-bindings/interrupt-controller/arm-gic.h> > > arm-gic.h includes irq.h. I prefer to explicitly #include what's needed, so I'd leave this alone if you don't mind... >> +#include <dt-bindings/clock/renesas-cpg-mssr.h> >> +#include <dt-bindings/power/r8a77970-sysc.h> > > You can avoid the dependency on the above header, which will go upstream > through a different branch, by hardcoding the power area indices for the > initial submission, like you already did for the CPG core clocks. OK. >> + >> +/ { >> + compatible = "renesas,r8a77970"; >> + #address-cells = <2>; >> + #size-cells = <2>; >> + >> + psci { >> + compatible = "arm,psci-1.0"; > > PSCI 1.0 is backwards compatible with PSI 0.2: > > compatible = "arm,psci-1.0", "arm,psci-0.2"; OK. > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > > Gr{oetje,eeting}s, > > Geert MBR, Sergei
Index: renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi =================================================================== --- /dev/null +++ renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi @@ -0,0 +1,126 @@ +/* + * Device Tree Source for the r8a77970 SoC + * + * Copyright (C) 2016-2017 Renesas Electronics Corp. + * Copyright (C) 2017 Cogent Embedded, Inc. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/renesas-cpg-mssr.h> +#include <dt-bindings/power/r8a77970-sysc.h> + +/ { + compatible = "renesas,r8a77970"; + #address-cells = <2>; + #size-cells = <2>; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + a53_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0>; + clocks = <&cpg CPG_CORE 0>; + power-domains = <&sysc R8A77970_PD_CA53_CPU0>; + next-level-cache = <&L2_CA53>; + enable-method = "psci"; + }; + + L2_CA53: cache-controller { + compatible = "cache"; + power-domains = <&sysc R8A77970_PD_CA53_SCU>; + cache-unified; + cache-level = <2>; + }; + }; + + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + extalr_clk: extalr { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gic: interrupt-controller@f1010000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0 0xf1010000 0 0x1000>, + <0 0xf1020000 0 0x20000>, + <0 0xf1040000 0 0x20000>, + <0 0xf1060000 0 0x20000>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | + IRQ_TYPE_LEVEL_HIGH)>; + clocks = <&cpg CPG_MOD 408>; + clock-names = "clk"; + power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; + resets = <&cpg 408>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | + IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | + IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | + IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | + IRQ_TYPE_LEVEL_LOW)>; + }; + + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a77970-cpg-mssr"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>, <&extalr_clk>; + clock-names = "extal", "extalr"; + #clock-cells = <2>; + #power-domain-cells = <0>; + #reset-cells = <1>; + }; + + rst: reset-controller@e6160000 { + compatible = "renesas,r8a77970-rst"; + reg = <0 0xe6160000 0 0x200>; + }; + + sysc: system-controller@e6180000 { + compatible = "renesas,r8a77970-sysc"; + reg = <0 0xe6180000 0 0x440>; + #power-domain-cells = <1>; + }; + + prr: chipid@fff00044 { + compatible = "renesas,prr"; + reg = <0 0xfff00044 0 4>; + }; + }; +};