| Message ID | 20170911174356.31cb7ef3@endymion (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Reviewed-by: Marek Olšák <marek.olsak@amd.com> Marek On Mon, Sep 11, 2017 at 5:43 PM, Jean Delvare <jdelvare@suse.de> wrote: > Several users have complained that the tile table update broke Oland > support. Despite several attempts to fix it, the root cause is still > unknown at this point and no solution is available. As it is not > acceptable to leave a known regression breaking a major functionality > in the kernel for several releases, let's just reverse this > optimization for now. It can be implemented again later if and only > if the breakage is understood and fixed. > > As there were no complaints for Hainan so far, only the Oland part of > the offending commit is reverted. Optimization is preserved on > Hainan, so this commit isn't an actual revert of the original. > > This fixes bug #194761: > https://bugzilla.kernel.org/show_bug.cgi?id=194761 > > Signed-off-by: Jean Delvare <jdelvare@suse.de> > Fixes: f8d9422ef80c ("drm/amdgpu: update tile table for oland/hainan") > Cc: Flora Cui <Flora.Cui@amd.com> > Cc: Junwei Zhang <Jerry.Zhang@amd.com> > Cc: Alex Deucher <alexander.deucher@amd.com> > Cc: Marek Olšák <maraeo@gmail.com> > --- > This version of the fix is suitable for kernels v4.13 and up. > I'm running it for some time now it works perfectly on my > Radeon R5 240 (Dell OEM): > 01:00.0 VGA compatible controller [0300]: Advanced Micro Devices, Inc. [AMD/ATI] Oland [Radeon HD 8570 / R7 240/340 OEM] [1002:6611] > > drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 189 +++++++++++++++++++++++++++++++++- > 1 file changed, 188 insertions(+), 1 deletion(-) > > --- linux-4.13.orig/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c 2017-09-11 17:33:30.103176910 +0200 > +++ linux-4.13/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c 2017-09-11 17:40:12.711316976 +0200 > @@ -636,7 +636,194 @@ static void gfx_v6_0_tiling_mode_table_i > NUM_BANKS(ADDR_SURF_2_BANK); > for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) > WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]); > - } else if (adev->asic_type == CHIP_OLAND || adev->asic_type == CHIP_HAINAN) { > + } else if (adev->asic_type == CHIP_OLAND) { > + tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | > + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | > + PIPE_CONFIG(ADDR_SURF_P4_8x16) | > + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | > + NUM_BANKS(ADDR_SURF_16_BANK) | > + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | > + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | > + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); > + tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | > + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | > + PIPE_CONFIG(ADDR_SURF_P4_8x16) | > + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | > + NUM_BANKS(ADDR_SURF_16_BANK) | > + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | > + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | > + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); > + tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | > + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | > + PIPE_CONFIG(ADDR_SURF_P4_8x16) | > + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | > + NUM_BANKS(ADDR_SURF_16_BANK) | > + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | > + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | > + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); > + tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | > + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | > + PIPE_CONFIG(ADDR_SURF_P4_8x16) | > + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | > + NUM_BANKS(ADDR_SURF_16_BANK) | > + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | > + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | > + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); > + tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | > + ARRAY_MODE(ARRAY_1D_TILED_THIN1) | > + PIPE_CONFIG(ADDR_SURF_P4_8x16) | > + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | > + NUM_BANKS(ADDR_SURF_16_BANK) | > + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | > + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | > + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); > + tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | > + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | > + PIPE_CONFIG(ADDR_SURF_P4_8x16) | > + TILE_SPLIT(split_equal_to_row_size) | > + NUM_BANKS(ADDR_SURF_16_BANK) | > + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | > + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | > + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); > + tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | > + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | > + PIPE_CONFIG(ADDR_SURF_P4_8x16) | > + TILE_SPLIT(split_equal_to_row_size) | > + NUM_BANKS(ADDR_SURF_16_BANK) | > + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | > + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | > + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); > + tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | > + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | > + PIPE_CONFIG(ADDR_SURF_P4_8x16) | > + TILE_SPLIT(split_equal_to_row_size) | > + NUM_BANKS(ADDR_SURF_16_BANK) | > + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | > + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | > + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); > + tilemode[8] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | > + ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | > + PIPE_CONFIG(ADDR_SURF_P4_8x16) | > + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | > + NUM_BANKS(ADDR_SURF_16_BANK) | > + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | > + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | > + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); > + tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | > + ARRAY_MODE(ARRAY_1D_TILED_THIN1) | > + PIPE_CONFIG(ADDR_SURF_P4_8x16) | > + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | > + NUM_BANKS(ADDR_SURF_16_BANK) | > + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | > + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | > + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); > + tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | > + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | > + PIPE_CONFIG(ADDR_SURF_P4_8x16) | > + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | > + NUM_BANKS(ADDR_SURF_16_BANK) | > + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | > + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | > + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); > + tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | > + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | > + PIPE_CONFIG(ADDR_SURF_P4_8x16) | > + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | > + NUM_BANKS(ADDR_SURF_16_BANK) | > + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | > + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | > + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); > + tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | > + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | > + PIPE_CONFIG(ADDR_SURF_P4_8x16) | > + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | > + NUM_BANKS(ADDR_SURF_16_BANK) | > + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | > + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | > + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); > + tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | > + ARRAY_MODE(ARRAY_1D_TILED_THIN1) | > + PIPE_CONFIG(ADDR_SURF_P4_8x16) | > + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | > + NUM_BANKS(ADDR_SURF_16_BANK) | > + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | > + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | > + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); > + tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | > + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | > + PIPE_CONFIG(ADDR_SURF_P4_8x16) | > + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | > + NUM_BANKS(ADDR_SURF_16_BANK) | > + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | > + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | > + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); > + tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | > + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | > + PIPE_CONFIG(ADDR_SURF_P4_8x16) | > + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | > + NUM_BANKS(ADDR_SURF_16_BANK) | > + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | > + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | > + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); > + tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | > + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | > + PIPE_CONFIG(ADDR_SURF_P4_8x16) | > + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | > + NUM_BANKS(ADDR_SURF_16_BANK) | > + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | > + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | > + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); > + tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | > + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | > + PIPE_CONFIG(ADDR_SURF_P4_8x16) | > + TILE_SPLIT(split_equal_to_row_size) | > + NUM_BANKS(ADDR_SURF_16_BANK) | > + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | > + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | > + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); > + tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | > + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | > + PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | > + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | > + NUM_BANKS(ADDR_SURF_16_BANK) | > + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | > + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | > + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); > + tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | > + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | > + PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | > + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | > + NUM_BANKS(ADDR_SURF_16_BANK) | > + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | > + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | > + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); > + tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | > + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | > + PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | > + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | > + NUM_BANKS(ADDR_SURF_16_BANK) | > + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | > + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | > + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); > + tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | > + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | > + PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | > + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | > + NUM_BANKS(ADDR_SURF_16_BANK) | > + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | > + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | > + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); > + tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | > + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | > + PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | > + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | > + NUM_BANKS(ADDR_SURF_8_BANK) | > + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | > + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | > + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1); > + for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) > + WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]); > + } else if (adev->asic_type == CHIP_HAINAN) { > tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | > ARRAY_MODE(ARRAY_2D_TILED_THIN1) | > PIPE_CONFIG(ADDR_SURF_P2) | > > > -- > Jean Delvare > SUSE L3 Support
On Thu, Sep 14, 2017 at 12:21 PM, Marek Olšák <maraeo@gmail.com> wrote: > Reviewed-by: Marek Olšák <marek.olsak@amd.com> Applied. thanks. Alex > > Marek > > On Mon, Sep 11, 2017 at 5:43 PM, Jean Delvare <jdelvare@suse.de> wrote: >> Several users have complained that the tile table update broke Oland >> support. Despite several attempts to fix it, the root cause is still >> unknown at this point and no solution is available. As it is not >> acceptable to leave a known regression breaking a major functionality >> in the kernel for several releases, let's just reverse this >> optimization for now. It can be implemented again later if and only >> if the breakage is understood and fixed. >> >> As there were no complaints for Hainan so far, only the Oland part of >> the offending commit is reverted. Optimization is preserved on >> Hainan, so this commit isn't an actual revert of the original. >> >> This fixes bug #194761: >> https://bugzilla.kernel.org/show_bug.cgi?id=194761 >> >> Signed-off-by: Jean Delvare <jdelvare@suse.de> >> Fixes: f8d9422ef80c ("drm/amdgpu: update tile table for oland/hainan") >> Cc: Flora Cui <Flora.Cui@amd.com> >> Cc: Junwei Zhang <Jerry.Zhang@amd.com> >> Cc: Alex Deucher <alexander.deucher@amd.com> >> Cc: Marek Olšák <maraeo@gmail.com> >> --- >> This version of the fix is suitable for kernels v4.13 and up. >> I'm running it for some time now it works perfectly on my >> Radeon R5 240 (Dell OEM): >> 01:00.0 VGA compatible controller [0300]: Advanced Micro Devices, Inc. [AMD/ATI] Oland [Radeon HD 8570 / R7 240/340 OEM] [1002:6611] >> >> drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 189 +++++++++++++++++++++++++++++++++- >> 1 file changed, 188 insertions(+), 1 deletion(-) >> >> --- linux-4.13.orig/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c 2017-09-11 17:33:30.103176910 +0200 >> +++ linux-4.13/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c 2017-09-11 17:40:12.711316976 +0200 >> @@ -636,7 +636,194 @@ static void gfx_v6_0_tiling_mode_table_i >> NUM_BANKS(ADDR_SURF_2_BANK); >> for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) >> WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]); >> - } else if (adev->asic_type == CHIP_OLAND || adev->asic_type == CHIP_HAINAN) { >> + } else if (adev->asic_type == CHIP_OLAND) { >> + tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | >> + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | >> + PIPE_CONFIG(ADDR_SURF_P4_8x16) | >> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | >> + NUM_BANKS(ADDR_SURF_16_BANK) | >> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | >> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | >> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); >> + tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | >> + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | >> + PIPE_CONFIG(ADDR_SURF_P4_8x16) | >> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | >> + NUM_BANKS(ADDR_SURF_16_BANK) | >> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | >> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | >> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); >> + tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | >> + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | >> + PIPE_CONFIG(ADDR_SURF_P4_8x16) | >> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | >> + NUM_BANKS(ADDR_SURF_16_BANK) | >> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | >> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | >> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); >> + tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | >> + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | >> + PIPE_CONFIG(ADDR_SURF_P4_8x16) | >> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | >> + NUM_BANKS(ADDR_SURF_16_BANK) | >> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | >> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | >> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); >> + tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | >> + ARRAY_MODE(ARRAY_1D_TILED_THIN1) | >> + PIPE_CONFIG(ADDR_SURF_P4_8x16) | >> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | >> + NUM_BANKS(ADDR_SURF_16_BANK) | >> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | >> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | >> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); >> + tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | >> + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | >> + PIPE_CONFIG(ADDR_SURF_P4_8x16) | >> + TILE_SPLIT(split_equal_to_row_size) | >> + NUM_BANKS(ADDR_SURF_16_BANK) | >> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | >> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | >> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); >> + tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | >> + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | >> + PIPE_CONFIG(ADDR_SURF_P4_8x16) | >> + TILE_SPLIT(split_equal_to_row_size) | >> + NUM_BANKS(ADDR_SURF_16_BANK) | >> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | >> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | >> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); >> + tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | >> + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | >> + PIPE_CONFIG(ADDR_SURF_P4_8x16) | >> + TILE_SPLIT(split_equal_to_row_size) | >> + NUM_BANKS(ADDR_SURF_16_BANK) | >> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | >> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | >> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); >> + tilemode[8] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | >> + ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | >> + PIPE_CONFIG(ADDR_SURF_P4_8x16) | >> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | >> + NUM_BANKS(ADDR_SURF_16_BANK) | >> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | >> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | >> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); >> + tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | >> + ARRAY_MODE(ARRAY_1D_TILED_THIN1) | >> + PIPE_CONFIG(ADDR_SURF_P4_8x16) | >> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | >> + NUM_BANKS(ADDR_SURF_16_BANK) | >> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | >> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | >> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); >> + tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | >> + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | >> + PIPE_CONFIG(ADDR_SURF_P4_8x16) | >> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | >> + NUM_BANKS(ADDR_SURF_16_BANK) | >> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | >> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | >> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); >> + tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | >> + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | >> + PIPE_CONFIG(ADDR_SURF_P4_8x16) | >> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | >> + NUM_BANKS(ADDR_SURF_16_BANK) | >> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | >> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | >> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); >> + tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | >> + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | >> + PIPE_CONFIG(ADDR_SURF_P4_8x16) | >> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | >> + NUM_BANKS(ADDR_SURF_16_BANK) | >> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | >> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | >> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); >> + tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | >> + ARRAY_MODE(ARRAY_1D_TILED_THIN1) | >> + PIPE_CONFIG(ADDR_SURF_P4_8x16) | >> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | >> + NUM_BANKS(ADDR_SURF_16_BANK) | >> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | >> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | >> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); >> + tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | >> + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | >> + PIPE_CONFIG(ADDR_SURF_P4_8x16) | >> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | >> + NUM_BANKS(ADDR_SURF_16_BANK) | >> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | >> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | >> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); >> + tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | >> + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | >> + PIPE_CONFIG(ADDR_SURF_P4_8x16) | >> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | >> + NUM_BANKS(ADDR_SURF_16_BANK) | >> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | >> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | >> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); >> + tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | >> + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | >> + PIPE_CONFIG(ADDR_SURF_P4_8x16) | >> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | >> + NUM_BANKS(ADDR_SURF_16_BANK) | >> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | >> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | >> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); >> + tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | >> + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | >> + PIPE_CONFIG(ADDR_SURF_P4_8x16) | >> + TILE_SPLIT(split_equal_to_row_size) | >> + NUM_BANKS(ADDR_SURF_16_BANK) | >> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | >> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | >> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); >> + tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | >> + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | >> + PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | >> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | >> + NUM_BANKS(ADDR_SURF_16_BANK) | >> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | >> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | >> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); >> + tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | >> + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | >> + PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | >> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | >> + NUM_BANKS(ADDR_SURF_16_BANK) | >> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | >> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | >> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); >> + tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | >> + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | >> + PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | >> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | >> + NUM_BANKS(ADDR_SURF_16_BANK) | >> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | >> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | >> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); >> + tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | >> + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | >> + PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | >> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | >> + NUM_BANKS(ADDR_SURF_16_BANK) | >> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | >> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | >> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); >> + tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | >> + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | >> + PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | >> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | >> + NUM_BANKS(ADDR_SURF_8_BANK) | >> + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | >> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | >> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1); >> + for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) >> + WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]); >> + } else if (adev->asic_type == CHIP_HAINAN) { >> tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | >> ARRAY_MODE(ARRAY_2D_TILED_THIN1) | >> PIPE_CONFIG(ADDR_SURF_P2) | >> >> >> -- >> Jean Delvare >> SUSE L3 Support > _______________________________________________ > dri-devel mailing list > dri-devel@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel
On Thu, 14 Sep 2017 12:31:29 -0400, Alex Deucher wrote: > On Thu, Sep 14, 2017 at 12:21 PM, Marek Olšák <maraeo@gmail.com> wrote: > > Reviewed-by: Marek Olšák <marek.olsak@amd.com> > > Applied. thanks. > > Alex Thanks. I forgot the tag but this is obviously a candidate for stable trees. I have prepared different version for older kernels already, I'll post it to stable@ after the fix is merged into Linus' tree.
--- linux-4.13.orig/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c 2017-09-11 17:33:30.103176910 +0200 +++ linux-4.13/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c 2017-09-11 17:40:12.711316976 +0200 @@ -636,7 +636,194 @@ static void gfx_v6_0_tiling_mode_table_i NUM_BANKS(ADDR_SURF_2_BANK); for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]); - } else if (adev->asic_type == CHIP_OLAND || adev->asic_type == CHIP_HAINAN) { + } else if (adev->asic_type == CHIP_OLAND) { + tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | + NUM_BANKS(ADDR_SURF_16_BANK) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); + tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | + NUM_BANKS(ADDR_SURF_16_BANK) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); + tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | + NUM_BANKS(ADDR_SURF_16_BANK) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); + tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | + NUM_BANKS(ADDR_SURF_16_BANK) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); + tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | + ARRAY_MODE(ARRAY_1D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | + NUM_BANKS(ADDR_SURF_16_BANK) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); + tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_8x16) | + TILE_SPLIT(split_equal_to_row_size) | + NUM_BANKS(ADDR_SURF_16_BANK) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); + tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_8x16) | + TILE_SPLIT(split_equal_to_row_size) | + NUM_BANKS(ADDR_SURF_16_BANK) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); + tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_8x16) | + TILE_SPLIT(split_equal_to_row_size) | + NUM_BANKS(ADDR_SURF_16_BANK) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); + tilemode[8] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | + ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | + PIPE_CONFIG(ADDR_SURF_P4_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | + NUM_BANKS(ADDR_SURF_16_BANK) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); + tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | + ARRAY_MODE(ARRAY_1D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | + NUM_BANKS(ADDR_SURF_16_BANK) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); + tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | + NUM_BANKS(ADDR_SURF_16_BANK) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); + tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | + NUM_BANKS(ADDR_SURF_16_BANK) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); + tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | + NUM_BANKS(ADDR_SURF_16_BANK) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); + tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | + ARRAY_MODE(ARRAY_1D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | + NUM_BANKS(ADDR_SURF_16_BANK) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); + tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | + NUM_BANKS(ADDR_SURF_16_BANK) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); + tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | + NUM_BANKS(ADDR_SURF_16_BANK) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); + tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | + NUM_BANKS(ADDR_SURF_16_BANK) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); + tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P4_8x16) | + TILE_SPLIT(split_equal_to_row_size) | + NUM_BANKS(ADDR_SURF_16_BANK) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); + tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | + NUM_BANKS(ADDR_SURF_16_BANK) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); + tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | + NUM_BANKS(ADDR_SURF_16_BANK) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4); + tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | + NUM_BANKS(ADDR_SURF_16_BANK) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); + tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | + NUM_BANKS(ADDR_SURF_16_BANK) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2); + tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | + ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | + NUM_BANKS(ADDR_SURF_8_BANK) | + BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1); + for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) + WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]); + } else if (adev->asic_type == CHIP_HAINAN) { tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | ARRAY_MODE(ARRAY_2D_TILED_THIN1) | PIPE_CONFIG(ADDR_SURF_P2) |
Several users have complained that the tile table update broke Oland support. Despite several attempts to fix it, the root cause is still unknown at this point and no solution is available. As it is not acceptable to leave a known regression breaking a major functionality in the kernel for several releases, let's just reverse this optimization for now. It can be implemented again later if and only if the breakage is understood and fixed. As there were no complaints for Hainan so far, only the Oland part of the offending commit is reverted. Optimization is preserved on Hainan, so this commit isn't an actual revert of the original. This fixes bug #194761: https://bugzilla.kernel.org/show_bug.cgi?id=194761 Signed-off-by: Jean Delvare <jdelvare@suse.de> Fixes: f8d9422ef80c ("drm/amdgpu: update tile table for oland/hainan") Cc: Flora Cui <Flora.Cui@amd.com> Cc: Junwei Zhang <Jerry.Zhang@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Marek Olšák <maraeo@gmail.com> --- This version of the fix is suitable for kernels v4.13 and up. I'm running it for some time now it works perfectly on my Radeon R5 240 (Dell OEM): 01:00.0 VGA compatible controller [0300]: Advanced Micro Devices, Inc. [AMD/ATI] Oland [Radeon HD 8570 / R7 240/340 OEM] [1002:6611] drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 189 +++++++++++++++++++++++++++++++++- 1 file changed, 188 insertions(+), 1 deletion(-)