| Message ID | 20170922173252.10137-20-matthew.auld@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 2017.09.22 18:32:50 +0100, Matthew Auld wrote: > Currently gvt gtt handling doesn't support huge page entries, so disable > for now. > > v2: remove useless 48b PPGTT check > > Suggested-by: Zhenyu Wang <zhenyuw@linux.intel.com> > Signed-off-by: Matthew Auld <matthew.auld@intel.com> > Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> > Cc: Chris Wilson <chris@chris-wilson.co.uk> > Cc: Zhenyu Wang <zhenyuw@linux.intel.com> > --- > drivers/gpu/drm/i915/i915_gem.c | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c > index 750c04002304..f98d8a08167b 100644 > --- a/drivers/gpu/drm/i915/i915_gem.c > +++ b/drivers/gpu/drm/i915/i915_gem.c > @@ -4831,6 +4831,14 @@ int i915_gem_init(struct drm_i915_private *dev_priv) > > mutex_lock(&dev_priv->drm.struct_mutex); > > + /* We need to fallback to 4K pages since gvt gtt handling doesn't > + * support huge page entries - we will need to check either hypervisor > + * mm can support huge guest page or just do emulation in gvt. > + */ > + if (intel_vgpu_active(dev_priv)) > + mkwrite_device_info(dev_priv)->page_sizes = > + I915_GTT_PAGE_SIZE_4K; > + > dev_priv->mm.unordered_timeline = dma_fence_context_alloc(1); > > if (!i915_modparams.enable_execlists) { > -- > 2.13.5 > Reviewed-by: Zhenyu Wang <zhenyuw@linux.intel.com> thanks
Quoting Matthew Auld (2017-09-22 18:32:50) > Currently gvt gtt handling doesn't support huge page entries, so disable > for now. > > v2: remove useless 48b PPGTT check > > Suggested-by: Zhenyu Wang <zhenyuw@linux.intel.com> > Signed-off-by: Matthew Auld <matthew.auld@intel.com> > Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> > Cc: Chris Wilson <chris@chris-wilson.co.uk> > Cc: Zhenyu Wang <zhenyuw@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> -Chris
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 750c04002304..f98d8a08167b 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -4831,6 +4831,14 @@ int i915_gem_init(struct drm_i915_private *dev_priv) mutex_lock(&dev_priv->drm.struct_mutex); + /* We need to fallback to 4K pages since gvt gtt handling doesn't + * support huge page entries - we will need to check either hypervisor + * mm can support huge guest page or just do emulation in gvt. + */ + if (intel_vgpu_active(dev_priv)) + mkwrite_device_info(dev_priv)->page_sizes = + I915_GTT_PAGE_SIZE_4K; + dev_priv->mm.unordered_timeline = dma_fence_context_alloc(1); if (!i915_modparams.enable_execlists) {
Currently gvt gtt handling doesn't support huge page entries, so disable for now. v2: remove useless 48b PPGTT check Suggested-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Matthew Auld <matthew.auld@intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Zhenyu Wang <zhenyuw@linux.intel.com> --- drivers/gpu/drm/i915/i915_gem.c | 8 ++++++++ 1 file changed, 8 insertions(+)