| Message ID | 20171012225447.256-5-michal.wajdeczko@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 10/13/2017 4:24 AM, Michal Wajdeczko wrote: > After Guc code reorg some documentation was left in wrong > place. Move it closer to corresponding definitions. > > Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> > Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> > Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com> Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com> nitpick: Can we use "GuC" or other preferred name consistently in all comments/commit message/subject except for tag for all GuC related changes. > --- > drivers/gpu/drm/i915/intel_guc.h | 11 +++++++++++ > drivers/gpu/drm/i915/intel_guc_loader.c | 23 ----------------------- > drivers/gpu/drm/i915/intel_uc_fw.h | 5 +++++ > 3 files changed, 16 insertions(+), 23 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h > index 8b44165..c7088a7 100644 > --- a/drivers/gpu/drm/i915/intel_guc.h > +++ b/drivers/gpu/drm/i915/intel_guc.h > @@ -33,6 +33,11 @@ > #include "i915_guc_reg.h" > #include "i915_vma.h" > > +/* > + * Top level structure of guc. It handles firmware loading and manages client > + * pool and doorbells. intel_guc owns a i915_guc_client to replace the legacy > + * ExecList submission. > + */ > struct intel_guc { > struct intel_uc_fw fw; > struct intel_guc_log log; > @@ -83,6 +88,12 @@ static inline void intel_guc_notify(struct intel_guc *guc) > guc->notify(guc); > } > > +/* > + * GuC does not allow any gfx GGTT address that falls into range [0, WOPCM_TOP), > + * which is reserved for Boot ROM, SRAM and WOPCM. Currently this top address is > + * 512K. In order to exclude 0-512K address space from GGTT, all gfx objects > + * used by GuC is pinned with PIN_OFFSET_BIAS along with size of WOPCM. > + */ > static inline u32 guc_ggtt_offset(struct i915_vma *vma) > { > u32 offset = i915_ggtt_offset(vma); > diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c > index d9089bc..8508b94 100644 > --- a/drivers/gpu/drm/i915/intel_guc_loader.c > +++ b/drivers/gpu/drm/i915/intel_guc_loader.c > @@ -29,29 +29,6 @@ > #include "i915_drv.h" > #include "intel_uc.h" > > -/** > - * DOC: GuC-specific firmware loader > - * > - * intel_guc: > - * Top level structure of guc. It handles firmware loading and manages client > - * pool and doorbells. intel_guc owns a i915_guc_client to replace the legacy > - * ExecList submission. > - * > - * Firmware versioning: > - * The firmware build process will generate a version header file with major and > - * minor version defined. The versions are built into CSS header of firmware. > - * i915 kernel driver set the minimal firmware version required per platform. > - * The firmware installation package will install (symbolic link) proper version > - * of firmware. > - * > - * GuC address space: > - * GuC does not allow any gfx GGTT address that falls into range [0, WOPCM_TOP), > - * which is reserved for Boot ROM, SRAM and WOPCM. Currently this top address is > - * 512K. In order to exclude 0-512K address space from GGTT, all gfx objects > - * used by GuC is pinned with PIN_OFFSET_BIAS along with size of WOPCM. > - * > - */ > - > #define SKL_FW_MAJOR 6 > #define SKL_FW_MINOR 1 > > diff --git a/drivers/gpu/drm/i915/intel_uc_fw.h b/drivers/gpu/drm/i915/intel_uc_fw.h > index c3e9af4..5c01849 100644 > --- a/drivers/gpu/drm/i915/intel_uc_fw.h > +++ b/drivers/gpu/drm/i915/intel_uc_fw.h > @@ -50,6 +50,11 @@ struct intel_uc_fw { > enum intel_uc_fw_status fetch_status; > enum intel_uc_fw_status load_status; > > + /* > + * The firmware build process will generate a version header file with major and > + * minor version defined. The versions are built into CSS header of firmware. > + * i915 kernel driver set the minimal firmware version required per platform. > + */ > u16 major_ver_wanted; > u16 minor_ver_wanted; > u16 major_ver_found;
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h index 8b44165..c7088a7 100644 --- a/drivers/gpu/drm/i915/intel_guc.h +++ b/drivers/gpu/drm/i915/intel_guc.h @@ -33,6 +33,11 @@ #include "i915_guc_reg.h" #include "i915_vma.h" +/* + * Top level structure of guc. It handles firmware loading and manages client + * pool and doorbells. intel_guc owns a i915_guc_client to replace the legacy + * ExecList submission. + */ struct intel_guc { struct intel_uc_fw fw; struct intel_guc_log log; @@ -83,6 +88,12 @@ static inline void intel_guc_notify(struct intel_guc *guc) guc->notify(guc); } +/* + * GuC does not allow any gfx GGTT address that falls into range [0, WOPCM_TOP), + * which is reserved for Boot ROM, SRAM and WOPCM. Currently this top address is + * 512K. In order to exclude 0-512K address space from GGTT, all gfx objects + * used by GuC is pinned with PIN_OFFSET_BIAS along with size of WOPCM. + */ static inline u32 guc_ggtt_offset(struct i915_vma *vma) { u32 offset = i915_ggtt_offset(vma); diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c index d9089bc..8508b94 100644 --- a/drivers/gpu/drm/i915/intel_guc_loader.c +++ b/drivers/gpu/drm/i915/intel_guc_loader.c @@ -29,29 +29,6 @@ #include "i915_drv.h" #include "intel_uc.h" -/** - * DOC: GuC-specific firmware loader - * - * intel_guc: - * Top level structure of guc. It handles firmware loading and manages client - * pool and doorbells. intel_guc owns a i915_guc_client to replace the legacy - * ExecList submission. - * - * Firmware versioning: - * The firmware build process will generate a version header file with major and - * minor version defined. The versions are built into CSS header of firmware. - * i915 kernel driver set the minimal firmware version required per platform. - * The firmware installation package will install (symbolic link) proper version - * of firmware. - * - * GuC address space: - * GuC does not allow any gfx GGTT address that falls into range [0, WOPCM_TOP), - * which is reserved for Boot ROM, SRAM and WOPCM. Currently this top address is - * 512K. In order to exclude 0-512K address space from GGTT, all gfx objects - * used by GuC is pinned with PIN_OFFSET_BIAS along with size of WOPCM. - * - */ - #define SKL_FW_MAJOR 6 #define SKL_FW_MINOR 1 diff --git a/drivers/gpu/drm/i915/intel_uc_fw.h b/drivers/gpu/drm/i915/intel_uc_fw.h index c3e9af4..5c01849 100644 --- a/drivers/gpu/drm/i915/intel_uc_fw.h +++ b/drivers/gpu/drm/i915/intel_uc_fw.h @@ -50,6 +50,11 @@ struct intel_uc_fw { enum intel_uc_fw_status fetch_status; enum intel_uc_fw_status load_status; + /* + * The firmware build process will generate a version header file with major and + * minor version defined. The versions are built into CSS header of firmware. + * i915 kernel driver set the minimal firmware version required per platform. + */ u16 major_ver_wanted; u16 minor_ver_wanted; u16 major_ver_found;
After Guc code reorg some documentation was left in wrong place. Move it closer to corresponding definitions. Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com> --- drivers/gpu/drm/i915/intel_guc.h | 11 +++++++++++ drivers/gpu/drm/i915/intel_guc_loader.c | 23 ----------------------- drivers/gpu/drm/i915/intel_uc_fw.h | 5 +++++ 3 files changed, 16 insertions(+), 23 deletions(-)