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[v4,2/2] dt-bindings: i2c: i2c-davinci: Update binding for 66AK2Gx pwr dm property

Message ID 20170911201145.31257-3-fcooper@ti.com (mailing list archive)
State New, archived
Headers show

Commit Message

Franklin Cooper Sept. 11, 2017, 8:11 p.m. UTC
Add pm-domains property which is required for 66AK2Gx. Also document 66AK2G
unique clocks property usage.

Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Sekhar Nori <nsekhar@ti.com>
---
 Documentation/devicetree/bindings/i2c/i2c-davinci.txt | 12 ++++++++++++
 1 file changed, 12 insertions(+)

Comments

Wolfram Sang Oct. 17, 2017, 9:46 p.m. UTC | #1
On Mon, Sep 11, 2017 at 03:11:45PM -0500, Franklin S Cooper Jr wrote:
> Add pm-domains property which is required for 66AK2Gx. Also document 66AK2G
> unique clocks property usage.
> 
> Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
> Acked-by: Rob Herring <robh@kernel.org>
> Acked-by: Sekhar Nori <nsekhar@ti.com>

Applied to for-next, thanks!
diff mbox

Patch

diff --git a/Documentation/devicetree/bindings/i2c/i2c-davinci.txt b/Documentation/devicetree/bindings/i2c/i2c-davinci.txt
index 5b123e0..64e6e65 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-davinci.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-davinci.txt
@@ -6,6 +6,18 @@  davinci/keystone i2c interface contains.
 Required properties:
 - compatible: "ti,davinci-i2c" or "ti,keystone-i2c";
 - reg : Offset and length of the register set for the device
+- clocks: I2C functional clock phandle.
+	  For 66AK2G this property should be set per binding,
+	  Documentation/devicetree/bindings/clock/ti,sci-clk.txt
+
+SoC-specific Required Properties:
+
+The following are mandatory properties for Keystone 2 66AK2G SoCs only:
+
+- power-domains:	Should contain a phandle to a PM domain provider node
+			and an args specifier containing the I2C device id
+			value. This property is as per the binding,
+			Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt
 
 Recommended properties :
 - interrupts : standard interrupt property.