diff mbox

[v2,4/4] arm64: dts: rockchip: add efuse for RK3368 SoCs

Message ID 20170904085119.25981-5-romain.perier@collabora.com (mailing list archive)
State Not Applicable, archived
Headers show

Commit Message

Romain Perier Sept. 4, 2017, 8:51 a.m. UTC
This adds the definition for eFuse that is found on RK3368 SoCs with the
corresponding data cells.

Signed-off-by: Romain Perier <romain.perier@collabora.com>
---
 arch/arm64/boot/dts/rockchip/rk3368.dtsi | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

Comments

Heiko Stuebner Oct. 24, 2017, 1:37 p.m. UTC | #1
Am Montag, 4. September 2017, 10:51:19 CEST schrieb Romain Perier:
> This adds the definition for eFuse that is found on RK3368 SoCs with the
> corresponding data cells.
> 
> Signed-off-by: Romain Perier <romain.perier@collabora.com>

applied for 4.15 after the following changes
- moved efuse node to its correct position (determined by register address)
- use correct clock-id as added by patch1 (efuse256 without the underscore)
- added the #address- and #size-cells properties for the subnodes
  to make dtc happy

Please pay a bit more attention for future patches.


Thanks
Heiko
--
To unsubscribe from this list: send the line "unsubscribe linux-clk" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
diff mbox

Patch

diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
index 3039c2da533e..cca2ce1705b3 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
@@ -569,6 +569,20 @@ 
 		};
 	};
 
+	efuse: efuse@ffb00000 {
+		compatible = "rockchip,rk3368-efuse";
+		reg = <0x0 0xffb00000 0x0 0x20>;
+		clocks = <&cru PCLK_EFUSE_256>;
+		clock-names = "pclk_efuse";
+
+		cpu_leakage: cpu-leakage@17 {
+			reg = <0x17 0x1>;
+		};
+		temp_adjust: temp-adjust@1f {
+			reg = <0x1f 0x1>;
+		};
+	};
+
 	tsadc: tsadc@ff280000 {
 		compatible = "rockchip,rk3368-tsadc";
 		reg = <0x0 0xff280000 0x0 0x100>;