| Message ID | 20171018135821.3248-5-deathsimple@vodafone.de (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Wed, Oct 18, 2017 at 9:58 AM, Christian König <ckoenig.leichtzumerken@gmail.com> wrote: > From: Christian König <christian.koenig@amd.com> > > Most BIOS don't enable this because of compatibility reasons. > > Manually enable a 64bit BAR of 64GB size so that we have > enough room for PCI devices. > > v2: style cleanups, increase size, add resource name, set correct flags, > print message that windows was added > v3: add defines for all the magic numbers, style cleanups > v4: add some comment that the BIOS should actually allow this using > _PRS and _SRS. > v5: only enable this if CONFIG_PHYS_ADDR_T_64BIT is set > > Signed-off-by: Christian König <christian.koenig@amd.com> > Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> > --- > arch/x86/pci/fixup.c | 80 ++++++++++++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 80 insertions(+) > > diff --git a/arch/x86/pci/fixup.c b/arch/x86/pci/fixup.c > index 11e407489db0..7b6bd76713c5 100644 > --- a/arch/x86/pci/fixup.c > +++ b/arch/x86/pci/fixup.c > @@ -618,3 +618,83 @@ static void quirk_apple_mbp_poweroff(struct pci_dev *pdev) > dev_info(dev, "can't work around MacBook Pro poweroff issue\n"); > } > DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8c10, quirk_apple_mbp_poweroff); > + > +#ifdef CONFIG_PHYS_ADDR_T_64BIT > + > +#define AMD_141b_MMIO_BASE(x) (0x80 + (x) * 0x8) > +#define AMD_141b_MMIO_BASE_RE_MASK BIT(0) > +#define AMD_141b_MMIO_BASE_WE_MASK BIT(1) > +#define AMD_141b_MMIO_BASE_MMIOBASE_MASK GENMASK(31,8) > + > +#define AMD_141b_MMIO_LIMIT(x) (0x84 + (x) * 0x8) > +#define AMD_141b_MMIO_LIMIT_MMIOLIMIT_MASK GENMASK(31,8) > + > +#define AMD_141b_MMIO_HIGH(x) (0x180 + (x) * 0x4) > +#define AMD_141b_MMIO_HIGH_MMIOBASE_MASK GENMASK(7,0) > +#define AMD_141b_MMIO_HIGH_MMIOLIMIT_SHIFT 16 > +#define AMD_141b_MMIO_HIGH_MMIOLIMIT_MASK GENMASK(23,16) > + > +/* > + * The PCI Firmware Spec, rev 3.2 notes that ACPI should optionally allow > + * configuring host bridge windows using the _PRS and _SRS methods. > + * > + * But this is rarely implemented, so we manually enable a large 64bit BAR for > + * PCIe device on AMD Family 15h (Models 30h-3fh) Processors here. > + */ > +static void pci_amd_enable_64bit_bar(struct pci_dev *dev) > +{ > + struct resource *res, *conflict; > + u32 base, limit, high; > + unsigned i; > + > + for (i = 0; i < 8; ++i) { > + pci_read_config_dword(dev, AMD_141b_MMIO_BASE(i), &base); > + pci_read_config_dword(dev, AMD_141b_MMIO_HIGH(i), &high); > + > + /* Is this slot free? */ > + if (!(base & (AMD_141b_MMIO_BASE_RE_MASK | > + AMD_141b_MMIO_BASE_WE_MASK))) > + break; > + > + base >>= 8; > + base |= high << 24; > + > + /* Abort if a slot already configures a 64bit BAR. */ > + if (base > 0x10000) > + return; > + } > + if (i == 8) > + return; > + > + res = kzalloc(sizeof(*res), GFP_KERNEL); > + if (!res) > + return; > + > + res->name = "PCI Bus 0000:00"; > + res->flags = IORESOURCE_PREFETCH | IORESOURCE_MEM | > + IORESOURCE_MEM_64 | IORESOURCE_WINDOW; > + res->start = 0x100000000ull; > + res->end = 0xfd00000000ull - 1; > + > + /* Just grab the free area behind system memory for this */ > + while ((conflict = request_resource_conflict(&iomem_resource, res))) > + res->start = conflict->end + 1; > + > + dev_info(&dev->dev, "adding root bus resource %pR\n", res); > + > + base = ((res->start >> 8) & AMD_141b_MMIO_BASE_MMIOBASE_MASK) | > + AMD_141b_MMIO_BASE_RE_MASK | AMD_141b_MMIO_BASE_WE_MASK; > + limit = ((res->end + 1) >> 8) & AMD_141b_MMIO_LIMIT_MMIOLIMIT_MASK; > + high = ((res->start >> 40) & AMD_141b_MMIO_HIGH_MMIOBASE_MASK) | > + ((((res->end + 1) >> 40) << AMD_141b_MMIO_HIGH_MMIOLIMIT_SHIFT) > + & AMD_141b_MMIO_HIGH_MMIOLIMIT_MASK); > + > + pci_write_config_dword(dev, AMD_141b_MMIO_HIGH(i), high); > + pci_write_config_dword(dev, AMD_141b_MMIO_LIMIT(i), limit); > + pci_write_config_dword(dev, AMD_141b_MMIO_BASE(i), base); > + > + pci_bus_add_resource(dev->bus, res, 0); > +} > +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x141b, pci_amd_enable_64bit_bar); > + We may want to expand this to cover more host bridges. E.g., on my KV system I have these: 00:00.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 15h (Models 30h-3fh) Processor Root Complex [1022:1422] 00:02.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Device [1022:1424] 00:03.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Device [1022:1424] 00:04.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Device [1022:1424] 00:18.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 15h (Models 30h-3fh) Processor Function 0 [1022:141a] 00:18.1 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 15h (Models 30h-3fh) Processor Function 1 [1022:141b] 00:18.2 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 15h (Models 30h-3fh) Processor Function 2 [1022:141c] 00:18.3 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 15h (Models 30h-3fh) Processor Function 3 [1022:141d] 00:18.4 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 15h (Models 30h-3fh) Processor Function 4 [1022:141e] 00:18.5 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Family 15h (Models 30h-3fh) Processor Function 5 [1022:141f] And on my CZ system: 00:00.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Device [1022:1576] 00:02.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Device [1022:157b] 00:03.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Device [1022:157b] 00:09.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Device [1022:157d] 00:18.0 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Device [1022:1570] 00:18.1 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Device [1022:1571] 00:18.2 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Device [1022:1572] 00:18.3 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Device [1022:1573] 00:18.4 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Device [1022:1574] 00:18.5 Host bridge [0600]: Advanced Micro Devices, Inc. [AMD] Device [1022:1575] Do you know if Zen based systems use the same registers? They have yet more set of pci ids for host bridges. Alex > +#endif > -- > 2.11.0 > > _______________________________________________ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx
On 10/18/2017 09:58 AM, Christian König wrote: > From: Christian König <christian.koenig@amd.com> > > Most BIOS don't enable this because of compatibility reasons. > > Manually enable a 64bit BAR of 64GB size so that we have > enough room for PCI devices. > > v2: style cleanups, increase size, add resource name, set correct flags, > print message that windows was added > v3: add defines for all the magic numbers, style cleanups > v4: add some comment that the BIOS should actually allow this using > _PRS and _SRS. > v5: only enable this if CONFIG_PHYS_ADDR_T_64BIT is set > > Signed-off-by: Christian König <christian.koenig@amd.com> > Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> > --- > arch/x86/pci/fixup.c | 80 ++++++++++++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 80 insertions(+) > > diff --git a/arch/x86/pci/fixup.c b/arch/x86/pci/fixup.c > index 11e407489db0..7b6bd76713c5 100644 > --- a/arch/x86/pci/fixup.c > +++ b/arch/x86/pci/fixup.c > @@ -618,3 +618,83 @@ static void quirk_apple_mbp_poweroff(struct pci_dev *pdev) > dev_info(dev, "can't work around MacBook Pro poweroff issue\n"); > } > DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8c10, quirk_apple_mbp_poweroff); > + > +#ifdef CONFIG_PHYS_ADDR_T_64BIT > + > +#define AMD_141b_MMIO_BASE(x) (0x80 + (x) * 0x8) > +#define AMD_141b_MMIO_BASE_RE_MASK BIT(0) > +#define AMD_141b_MMIO_BASE_WE_MASK BIT(1) > +#define AMD_141b_MMIO_BASE_MMIOBASE_MASK GENMASK(31,8) > + > +#define AMD_141b_MMIO_LIMIT(x) (0x84 + (x) * 0x8) > +#define AMD_141b_MMIO_LIMIT_MMIOLIMIT_MASK GENMASK(31,8) > + > +#define AMD_141b_MMIO_HIGH(x) (0x180 + (x) * 0x4) > +#define AMD_141b_MMIO_HIGH_MMIOBASE_MASK GENMASK(7,0) > +#define AMD_141b_MMIO_HIGH_MMIOLIMIT_SHIFT 16 > +#define AMD_141b_MMIO_HIGH_MMIOLIMIT_MASK GENMASK(23,16) > + > +/* > + * The PCI Firmware Spec, rev 3.2 notes that ACPI should optionally allow > + * configuring host bridge windows using the _PRS and _SRS methods. > + * > + * But this is rarely implemented, so we manually enable a large 64bit BAR for > + * PCIe device on AMD Family 15h (Models 30h-3fh) Processors here. > + */ > +static void pci_amd_enable_64bit_bar(struct pci_dev *dev) > +{ > + struct resource *res, *conflict; > + u32 base, limit, high; > + unsigned i; > + > + for (i = 0; i < 8; ++i) { > + pci_read_config_dword(dev, AMD_141b_MMIO_BASE(i), &base); > + pci_read_config_dword(dev, AMD_141b_MMIO_HIGH(i), &high); > + > + /* Is this slot free? */ > + if (!(base & (AMD_141b_MMIO_BASE_RE_MASK | > + AMD_141b_MMIO_BASE_WE_MASK))) > + break; > + > + base >>= 8; > + base |= high << 24; > + > + /* Abort if a slot already configures a 64bit BAR. */ > + if (base > 0x10000) > + return; > + } > + if (i == 8) > + return; > + > + res = kzalloc(sizeof(*res), GFP_KERNEL); > + if (!res) > + return; > + > + res->name = "PCI Bus 0000:00"; > + res->flags = IORESOURCE_PREFETCH | IORESOURCE_MEM | > + IORESOURCE_MEM_64 | IORESOURCE_WINDOW; > + res->start = 0x100000000ull; > + res->end = 0xfd00000000ull - 1; > + > + /* Just grab the free area behind system memory for this */ > + while ((conflict = request_resource_conflict(&iomem_resource, res))) > + res->start = conflict->end + 1; I get stuck in the infinite loop here. Presumably because on a multi-socket system we succeed for the first processor (0000:00:18.1) and add 'res' to iomem_resource. For 0000:00:19.1 we find the slot in the 'for' loop above but then we fail to find a place to add 'res'. And with final sibling being [0 - max possible addr] we are stuck here. A possible solution to get out of the loop could be if (conflict->end >= res->end) { kfree(res); return; } but I don't know whether this is what we actually want. This is a 2-socket vendor_id : AuthenticAMD cpu family : 21 model : 1 model name : AMD Opteron(TM) Processor 6272 stepping : 2 (and then it breaks differently as a Xen guest --- we hung on the last pci_read_config_dword(), I haven't looked at this at all yet) -boris > + > + dev_info(&dev->dev, "adding root bus resource %pR\n", res); > + > + base = ((res->start >> 8) & AMD_141b_MMIO_BASE_MMIOBASE_MASK) | > + AMD_141b_MMIO_BASE_RE_MASK | AMD_141b_MMIO_BASE_WE_MASK; > + limit = ((res->end + 1) >> 8) & AMD_141b_MMIO_LIMIT_MMIOLIMIT_MASK; > + high = ((res->start >> 40) & AMD_141b_MMIO_HIGH_MMIOBASE_MASK) | > + ((((res->end + 1) >> 40) << AMD_141b_MMIO_HIGH_MMIOLIMIT_SHIFT) > + & AMD_141b_MMIO_HIGH_MMIOLIMIT_MASK); > + > + pci_write_config_dword(dev, AMD_141b_MMIO_HIGH(i), high); > + pci_write_config_dword(dev, AMD_141b_MMIO_LIMIT(i), limit); > + pci_write_config_dword(dev, AMD_141b_MMIO_BASE(i), base); > + > + pci_bus_add_resource(dev->bus, res, 0); > +} > +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x141b, pci_amd_enable_64bit_bar); > + > +#endif
Am 20.11.2017 um 16:51 schrieb Boris Ostrovsky: > On 10/18/2017 09:58 AM, Christian König wrote: >> From: Christian König <christian.koenig@amd.com> >> >> Most BIOS don't enable this because of compatibility reasons. >> >> Manually enable a 64bit BAR of 64GB size so that we have >> enough room for PCI devices. >> >> v2: style cleanups, increase size, add resource name, set correct flags, >> print message that windows was added >> v3: add defines for all the magic numbers, style cleanups >> v4: add some comment that the BIOS should actually allow this using >> _PRS and _SRS. >> v5: only enable this if CONFIG_PHYS_ADDR_T_64BIT is set >> >> Signed-off-by: Christian König <christian.koenig@amd.com> >> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> >> --- >> arch/x86/pci/fixup.c | 80 ++++++++++++++++++++++++++++++++++++++++++++++++++++ >> 1 file changed, 80 insertions(+) >> >> diff --git a/arch/x86/pci/fixup.c b/arch/x86/pci/fixup.c >> index 11e407489db0..7b6bd76713c5 100644 >> --- a/arch/x86/pci/fixup.c >> +++ b/arch/x86/pci/fixup.c >> @@ -618,3 +618,83 @@ static void quirk_apple_mbp_poweroff(struct pci_dev *pdev) >> dev_info(dev, "can't work around MacBook Pro poweroff issue\n"); >> } >> DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8c10, quirk_apple_mbp_poweroff); >> + >> +#ifdef CONFIG_PHYS_ADDR_T_64BIT >> + >> +#define AMD_141b_MMIO_BASE(x) (0x80 + (x) * 0x8) >> +#define AMD_141b_MMIO_BASE_RE_MASK BIT(0) >> +#define AMD_141b_MMIO_BASE_WE_MASK BIT(1) >> +#define AMD_141b_MMIO_BASE_MMIOBASE_MASK GENMASK(31,8) >> + >> +#define AMD_141b_MMIO_LIMIT(x) (0x84 + (x) * 0x8) >> +#define AMD_141b_MMIO_LIMIT_MMIOLIMIT_MASK GENMASK(31,8) >> + >> +#define AMD_141b_MMIO_HIGH(x) (0x180 + (x) * 0x4) >> +#define AMD_141b_MMIO_HIGH_MMIOBASE_MASK GENMASK(7,0) >> +#define AMD_141b_MMIO_HIGH_MMIOLIMIT_SHIFT 16 >> +#define AMD_141b_MMIO_HIGH_MMIOLIMIT_MASK GENMASK(23,16) >> + >> +/* >> + * The PCI Firmware Spec, rev 3.2 notes that ACPI should optionally allow >> + * configuring host bridge windows using the _PRS and _SRS methods. >> + * >> + * But this is rarely implemented, so we manually enable a large 64bit BAR for >> + * PCIe device on AMD Family 15h (Models 30h-3fh) Processors here. >> + */ >> +static void pci_amd_enable_64bit_bar(struct pci_dev *dev) >> +{ >> + struct resource *res, *conflict; >> + u32 base, limit, high; >> + unsigned i; >> + >> + for (i = 0; i < 8; ++i) { >> + pci_read_config_dword(dev, AMD_141b_MMIO_BASE(i), &base); >> + pci_read_config_dword(dev, AMD_141b_MMIO_HIGH(i), &high); >> + >> + /* Is this slot free? */ >> + if (!(base & (AMD_141b_MMIO_BASE_RE_MASK | >> + AMD_141b_MMIO_BASE_WE_MASK))) >> + break; >> + >> + base >>= 8; >> + base |= high << 24; >> + >> + /* Abort if a slot already configures a 64bit BAR. */ >> + if (base > 0x10000) >> + return; >> + } >> + if (i == 8) >> + return; >> + >> + res = kzalloc(sizeof(*res), GFP_KERNEL); >> + if (!res) >> + return; >> + >> + res->name = "PCI Bus 0000:00"; >> + res->flags = IORESOURCE_PREFETCH | IORESOURCE_MEM | >> + IORESOURCE_MEM_64 | IORESOURCE_WINDOW; >> + res->start = 0x100000000ull; >> + res->end = 0xfd00000000ull - 1; >> + >> + /* Just grab the free area behind system memory for this */ >> + while ((conflict = request_resource_conflict(&iomem_resource, res))) >> + res->start = conflict->end + 1; > > I get stuck in the infinite loop here. > > Presumably because on a multi-socket system we succeed for the first > processor (0000:00:18.1) and add 'res' to iomem_resource. For > 0000:00:19.1 we find the slot in the 'for' loop above but then we fail > to find a place to add 'res'. And with final sibling being [0 - max > possible addr] we are stuck here. > > A possible solution to get out of the loop could be > if (conflict->end >= res->end) { > kfree(res); > return; > } Ah, sorry for that. Yes problem is obvious now. > but I don't know whether this is what we actually want. Actually we would probably want to add the range to all cores at the same time. > > This is a 2-socket > > vendor_id : AuthenticAMD > cpu family : 21 > model : 1 > model name : AMD Opteron(TM) Processor 6272 > stepping : 2 > > > (and then it breaks differently as a Xen guest --- we hung on the last > pci_read_config_dword(), I haven't looked at this at all yet) Hui? How does this fix applies to a Xen guest in the first place? Please provide the output of "lspci -nn" and explain further what is your config with Xen. Regards, Christian. > > > > -boris > > >> + >> + dev_info(&dev->dev, "adding root bus resource %pR\n", res); >> + >> + base = ((res->start >> 8) & AMD_141b_MMIO_BASE_MMIOBASE_MASK) | >> + AMD_141b_MMIO_BASE_RE_MASK | AMD_141b_MMIO_BASE_WE_MASK; >> + limit = ((res->end + 1) >> 8) & AMD_141b_MMIO_LIMIT_MMIOLIMIT_MASK; >> + high = ((res->start >> 40) & AMD_141b_MMIO_HIGH_MMIOBASE_MASK) | >> + ((((res->end + 1) >> 40) << AMD_141b_MMIO_HIGH_MMIOLIMIT_SHIFT) >> + & AMD_141b_MMIO_HIGH_MMIOLIMIT_MASK); >> + >> + pci_write_config_dword(dev, AMD_141b_MMIO_HIGH(i), high); >> + pci_write_config_dword(dev, AMD_141b_MMIO_LIMIT(i), limit); >> + pci_write_config_dword(dev, AMD_141b_MMIO_BASE(i), base); >> + >> + pci_bus_add_resource(dev->bus, res, 0); >> +} >> +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x141b, pci_amd_enable_64bit_bar); >> + >> +#endif
On 11/20/2017 11:07 AM, Christian König wrote: > Am 20.11.2017 um 16:51 schrieb Boris Ostrovsky: >> >> (and then it breaks differently as a Xen guest --- we hung on the last >> pci_read_config_dword(), I haven't looked at this at all yet) > > Hui? How does this fix applies to a Xen guest in the first place? > > Please provide the output of "lspci -nn" and explain further what is > your config with Xen. > > This is dom0. -bash-4.1# lspci -nn 00:00.0 Host bridge [0600]: ATI Technologies Inc RD890 Northbridge only dual slot (2x16) PCI-e GFX Hydra part [1002:5a10] (rev 02) 00:00.2 Generic system peripheral [0806]: ATI Technologies Inc Device [1002:5a23] 00:0d.0 PCI bridge [0604]: ATI Technologies Inc RD890 PCI to PCI bridge (external gfx1 port B) [1002:5a1e] 00:11.0 SATA controller [0106]: ATI Technologies Inc SB700/SB800 SATA Controller [AHCI mode] [1002:4391] 00:12.0 USB Controller [0c03]: ATI Technologies Inc SB700/SB800 USB OHCI0 Controller [1002:4397] 00:12.1 USB Controller [0c03]: ATI Technologies Inc SB700 USB OHCI1 Controller [1002:4398] 00:12.2 USB Controller [0c03]: ATI Technologies Inc SB700/SB800 USB EHCI Controller [1002:4396] 00:13.0 USB Controller [0c03]: ATI Technologies Inc SB700/SB800 USB OHCI0 Controller [1002:4397] 00:13.1 USB Controller [0c03]: ATI Technologies Inc SB700 USB OHCI1 Controller [1002:4398] 00:13.2 USB Controller [0c03]: ATI Technologies Inc SB700/SB800 USB EHCI Controller [1002:4396] 00:14.0 SMBus [0c05]: ATI Technologies Inc SBx00 SMBus Controller [1002:4385] (rev 3d) 00:14.3 ISA bridge [0601]: ATI Technologies Inc SB700/SB800 LPC host controller [1002:439d] 00:14.4 PCI bridge [0604]: ATI Technologies Inc SBx00 PCI to PCI Bridge [1002:4384] 00:14.5 USB Controller [0c03]: ATI Technologies Inc SB700/SB800 USB OHCI2 Controller [1002:4399] 00:18.0 Host bridge [0600]: Advanced Micro Devices [AMD] Device [1022:1600] 00:18.1 Host bridge [0600]: Advanced Micro Devices [AMD] Device [1022:1601] 00:18.2 Host bridge [0600]: Advanced Micro Devices [AMD] Device [1022:1602] 00:18.3 Host bridge [0600]: Advanced Micro Devices [AMD] Device [1022:1603] 00:18.4 Host bridge [0600]: Advanced Micro Devices [AMD] Device [1022:1604] 00:18.5 Host bridge [0600]: Advanced Micro Devices [AMD] Device [1022:1605] 00:19.0 Host bridge [0600]: Advanced Micro Devices [AMD] Device [1022:1600] 00:19.1 Host bridge [0600]: Advanced Micro Devices [AMD] Device [1022:1601] 00:19.2 Host bridge [0600]: Advanced Micro Devices [AMD] Device [1022:1602] 00:19.3 Host bridge [0600]: Advanced Micro Devices [AMD] Device [1022:1603] 00:19.4 Host bridge [0600]: Advanced Micro Devices [AMD] Device [1022:1604] 00:19.5 Host bridge [0600]: Advanced Micro Devices [AMD] Device [1022:1605] 01:04.0 VGA compatible controller [0300]: Matrox Graphics, Inc. MGA G200eW WPCM450 [102b:0532] (rev 0a) 02:00.0 Ethernet controller [0200]: Intel Corporation 82576 Gigabit Network Connection [8086:10c9] (rev 01) 02:00.1 Ethernet controller [0200]: Intel Corporation 82576 Gigabit Network Connection [8086:10c9] (rev 01) -bash-4.1# -boris
diff --git a/arch/x86/pci/fixup.c b/arch/x86/pci/fixup.c index 11e407489db0..7b6bd76713c5 100644 --- a/arch/x86/pci/fixup.c +++ b/arch/x86/pci/fixup.c @@ -618,3 +618,83 @@ static void quirk_apple_mbp_poweroff(struct pci_dev *pdev) dev_info(dev, "can't work around MacBook Pro poweroff issue\n"); } DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8c10, quirk_apple_mbp_poweroff); + +#ifdef CONFIG_PHYS_ADDR_T_64BIT + +#define AMD_141b_MMIO_BASE(x) (0x80 + (x) * 0x8) +#define AMD_141b_MMIO_BASE_RE_MASK BIT(0) +#define AMD_141b_MMIO_BASE_WE_MASK BIT(1) +#define AMD_141b_MMIO_BASE_MMIOBASE_MASK GENMASK(31,8) + +#define AMD_141b_MMIO_LIMIT(x) (0x84 + (x) * 0x8) +#define AMD_141b_MMIO_LIMIT_MMIOLIMIT_MASK GENMASK(31,8) + +#define AMD_141b_MMIO_HIGH(x) (0x180 + (x) * 0x4) +#define AMD_141b_MMIO_HIGH_MMIOBASE_MASK GENMASK(7,0) +#define AMD_141b_MMIO_HIGH_MMIOLIMIT_SHIFT 16 +#define AMD_141b_MMIO_HIGH_MMIOLIMIT_MASK GENMASK(23,16) + +/* + * The PCI Firmware Spec, rev 3.2 notes that ACPI should optionally allow + * configuring host bridge windows using the _PRS and _SRS methods. + * + * But this is rarely implemented, so we manually enable a large 64bit BAR for + * PCIe device on AMD Family 15h (Models 30h-3fh) Processors here. + */ +static void pci_amd_enable_64bit_bar(struct pci_dev *dev) +{ + struct resource *res, *conflict; + u32 base, limit, high; + unsigned i; + + for (i = 0; i < 8; ++i) { + pci_read_config_dword(dev, AMD_141b_MMIO_BASE(i), &base); + pci_read_config_dword(dev, AMD_141b_MMIO_HIGH(i), &high); + + /* Is this slot free? */ + if (!(base & (AMD_141b_MMIO_BASE_RE_MASK | + AMD_141b_MMIO_BASE_WE_MASK))) + break; + + base >>= 8; + base |= high << 24; + + /* Abort if a slot already configures a 64bit BAR. */ + if (base > 0x10000) + return; + } + if (i == 8) + return; + + res = kzalloc(sizeof(*res), GFP_KERNEL); + if (!res) + return; + + res->name = "PCI Bus 0000:00"; + res->flags = IORESOURCE_PREFETCH | IORESOURCE_MEM | + IORESOURCE_MEM_64 | IORESOURCE_WINDOW; + res->start = 0x100000000ull; + res->end = 0xfd00000000ull - 1; + + /* Just grab the free area behind system memory for this */ + while ((conflict = request_resource_conflict(&iomem_resource, res))) + res->start = conflict->end + 1; + + dev_info(&dev->dev, "adding root bus resource %pR\n", res); + + base = ((res->start >> 8) & AMD_141b_MMIO_BASE_MMIOBASE_MASK) | + AMD_141b_MMIO_BASE_RE_MASK | AMD_141b_MMIO_BASE_WE_MASK; + limit = ((res->end + 1) >> 8) & AMD_141b_MMIO_LIMIT_MMIOLIMIT_MASK; + high = ((res->start >> 40) & AMD_141b_MMIO_HIGH_MMIOBASE_MASK) | + ((((res->end + 1) >> 40) << AMD_141b_MMIO_HIGH_MMIOLIMIT_SHIFT) + & AMD_141b_MMIO_HIGH_MMIOLIMIT_MASK); + + pci_write_config_dword(dev, AMD_141b_MMIO_HIGH(i), high); + pci_write_config_dword(dev, AMD_141b_MMIO_LIMIT(i), limit); + pci_write_config_dword(dev, AMD_141b_MMIO_BASE(i), base); + + pci_bus_add_resource(dev->bus, res, 0); +} +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x141b, pci_amd_enable_64bit_bar); + +#endif