| Message ID | 20171113154126.13038-4-george.dunlap@citrix.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
>>> On 13.11.17 at 16:41, <george.dunlap@citrix.com> wrote: > +### ARM/SMMUv1 > + > + Status: Supported > + > +### ARM/SMMUv2 > + > + Status: Supported Do these belong here, when IOMMU isn't part of the corresponding x86 patch? Jan
On 11/21/2017 08:11 AM, Jan Beulich wrote: >>>> On 13.11.17 at 16:41, <george.dunlap@citrix.com> wrote: >> +### ARM/SMMUv1 >> + >> + Status: Supported >> + >> +### ARM/SMMUv2 >> + >> + Status: Supported > > Do these belong here, when IOMMU isn't part of the corresponding > x86 patch? Since there was recently a time when these weren't supported, I think it's useful to have them in here. (Julien, let me know if you think otherwise.) Do you think it would be useful to include an IOMMU line for x86? -George
Hi George, On 11/21/2017 10:45 AM, George Dunlap wrote: > On 11/21/2017 08:11 AM, Jan Beulich wrote: >>>>> On 13.11.17 at 16:41, <george.dunlap@citrix.com> wrote: >>> +### ARM/SMMUv1 >>> + >>> + Status: Supported >>> + >>> +### ARM/SMMUv2 >>> + >>> + Status: Supported >> >> Do these belong here, when IOMMU isn't part of the corresponding >> x86 patch? > > Since there was recently a time when these weren't supported, I think > it's useful to have them in here. (Julien, let me know if you think > otherwise.) I think it is useful to keep them. There are other IOMMUs existing on Arm (e.g SMMUv3, IPMMU-VMSA) that we don't yet support in Xen. Cheers,
>>> On 21.11.17 at 11:45, <george.dunlap@citrix.com> wrote: > On 11/21/2017 08:11 AM, Jan Beulich wrote: >>>>> On 13.11.17 at 16:41, <george.dunlap@citrix.com> wrote: >>> +### ARM/SMMUv1 >>> + >>> + Status: Supported >>> + >>> +### ARM/SMMUv2 >>> + >>> + Status: Supported >> >> Do these belong here, when IOMMU isn't part of the corresponding >> x86 patch? > > Since there was recently a time when these weren't supported, I think > it's useful to have them in here. (Julien, let me know if you think > otherwise.) > > Do you think it would be useful to include an IOMMU line for x86? At this point of the series I would surely have said "yes". The later PCI passthrough additions state this implicitly at least (by requiring an IOMMU for passthrough to be supported at all). But even then saying so explicitly may be better. Jan
On Nov 21, 2017, at 11:37 AM, Jan Beulich <JBeulich@suse.com<mailto:JBeulich@suse.com>> wrote:
On 21.11.17 at 11:45, <george.dunlap@citrix.com<mailto:george.dunlap@citrix.com>> wrote:
On 11/21/2017 08:11 AM, Jan Beulich wrote:
On 13.11.17 at 16:41, <george.dunlap@citrix.com<mailto:george.dunlap@citrix.com>> wrote:
+### ARM/SMMUv1
+
+ Status: Supported
+
+### ARM/SMMUv2
+
+ Status: Supported
Do these belong here, when IOMMU isn't part of the corresponding
x86 patch?
Since there was recently a time when these weren't supported, I think
it's useful to have them in here. (Julien, let me know if you think
otherwise.)
Do you think it would be useful to include an IOMMU line for x86?
At this point of the series I would surely have said "yes". The
later PCI passthrough additions state this implicitly at least (by
requiring an IOMMU for passthrough to be supported at all).
But even then saying so explicitly may be better.
How much do we specifically need to break down? AMD / Intel?
What about something like this?
### IOMMU
Status, AMD IOMMU: Supported
Status, Intel VT-d: Supported
Status, ARM SMMUv1: Supported
Status, ARM SMMUv2: Supported
-George
>>> On 21.11.17 at 13:39, <George.Dunlap@citrix.com> wrote: > What about something like this? > > ### IOMMU > > Status, AMD IOMMU: Supported > Status, Intel VT-d: Supported > Status, ARM SMMUv1: Supported > Status, ARM SMMUv2: Supported Fine with me, as it makes things explicit. Jan
diff --git a/SUPPORT.md b/SUPPORT.md index 6b09f98331..7c01d8cf9a 100644 --- a/SUPPORT.md +++ b/SUPPORT.md @@ -22,6 +22,14 @@ for the definitions of the support status levels etc. Status: Supported +### ARM v7 + Virtualization Extensions + + Status: Supported + +### ARM v8 + + Status: Supported + ## Host hardware support ### Physical CPU Hotplug @@ -36,11 +44,26 @@ for the definitions of the support status levels etc. Status, x86 PV: Supported Status, x86 PVH: Tech preview + Status, ARM: Experimental ### x86/Intel Platform QoS Technologies Status: Tech Preview +### ARM/SMMUv1 + + Status: Supported + +### ARM/SMMUv2 + + Status: Supported + +### ARM/GICv3 ITS + + Status: Experimental + +Extension to the GICv3 interrupt controller to support MSI. + ## Guest Type ### x86/PV @@ -69,6 +92,12 @@ During development this was sometimes called HVMLite or PVHv2. Requires hardware virtualisation support (Intel VMX / AMD SVM) +### ARM guest + + Status: Supported + +ARM only has one guest type at the moment + ## Memory Management ### Memory Ballooning
Hardware support and guest type. Signed-off-by: George Dunlap <george.dunlap@citrix.com> --- CC: Ian Jackson <ian.jackson@citrix.com> CC: Wei Liu <wei.liu2@citrix.com> CC: Andrew Cooper <andrew.cooper3@citrix.com> CC: Jan Beulich <jbeulich@suse.com> CC: Stefano Stabellini <sstabellini@kernel.org> CC: Konrad Wilk <konrad.wilk@oracle.com> CC: Tim Deegan <tim@xen.org> CC: Julien Grall <julien.grall@arm.com> --- SUPPORT.md | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+)